diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspUpd.h | 74 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 267 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 244 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 15 |
4 files changed, 381 insertions, 219 deletions
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h index 46fb08042e..61d03a2901 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h @@ -1,42 +1,42 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FSP_API_H_ -#define _FSP_API_H_ - -/** FSP UPD Header -**/ -struct FSP_UPD_HEADER { +/** @file -/** Offset 0x00 to 0x07 - UPD Region Signature - The signature will be - "FSPT_UPD" for FSP-T - "FSPM_UPD" for FSP-M - "FSPS_UPD" for FSP-S -**/ - uint64_t Signature; +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> -/** Offset 0x08 - Revision -**/ - uint8_t Revision; +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! -/** Offset 0x09 to 0x1F - ReservedUpd **/ - uint8_t ReservedUpd[23]; -} __attribute__((packed)); -#endif /* _FSP_API_H_ */ +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#define FSPT_UPD_SIGNATURE 0x4450555F54505346 /* 'FSPT_UPD' */ + +#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ + +#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ + +#endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index b1a16072e5..906f6a4bb6 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -34,111 +34,28 @@ are permitted provided that the following conditions are met: #define __FSPMUPD_H__ #include "FspUpd.h" - - -typedef union { - uint32_t PadCnf0; - struct { - uint32_t GPIOTxState:1; ///< 0 GPIO TX State - uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO - uint32_t Reserved1:6; ///< 2-7 Reserved, RO - uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8] - uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc. - uint32_t Reserved2:4; ///< 13-16 Reserved, RO - uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17] - uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO - uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion - uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT - uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge - uint32_t Reserved3:1; ///< 27 RO - uint32_t RXRAW1:1; ///< 28 Override the RX to 1 - uint32_t RXPadStSel:1; ///< 29 RX Pad State Select - uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config - } r; -} BL_CONF_PAD0; - -typedef union { - uint32_t PadCnf1; - struct { - uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO - uint32_t Reserved:1; ///< 7 Reserved. - uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW - uint32_t Term:4; ///< 10-13 Termination, - ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu; - ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination - uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW - uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO - } r; -} BL_CONF_PAD1; - -struct BL_GPIO_PAD_INIT { - BL_CONF_PAD0 PadConfg0; - BL_CONF_PAD1 PadConfg1; - uint8_t Community; - uint16_t MmioAddress; - bool HostSw; - bool WakeEnabled; - wchar_t *PadName; -} __attribute__((packed)); - -/** Fsp M Architectural UPD -**/ -struct FSP_M_ARCH_UPD { - -/** Offset 0x0020 -**/ - uint8_t Revision; - -/** Offset 0x0021 -**/ - uint8_t Reserved[3]; - -/** Offset 0x0024 -**/ - void* NvsBufferPtr; - -/** Offset 0x0028 - StackBase - To hold the stack base. -**/ - void* StackBase; - -/** Offset 0x002C - StackSize - To hold the stack size. -**/ - uint32_t StackSize; - -/** Offset 0x0030 - BootLoaderTolumSize - To pass Bootloader Tolum size. -**/ - uint32_t BootLoaderTolumSize; - -/** Offset 0x0034 - Bootmode - To maintain Bootmode details. -**/ - uint32_t Bootmode; - -/** Offset 0x0038 -**/ - uint8_t Reserved1[8]; -} __attribute__((packed)); +#include <fsp/upd.h> /** Fsp M Configuration **/ struct FSP_M_CONFIG { /** Offset 0x0040 - Debug Serial Port Base address - Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. 0x00000000(Default). + Debug serial port base address. This option will be used only when the 'Serial Port + Debug Device' option is set to 'External Device'. 0x00000000(Default). **/ uint32_t SerialDebugPortAddress; /** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. 0x02:MMIO(Default). + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0x02:MMIO(Default). 0:NONE, 1:I/O, 2:MMIO **/ uint8_t SerialDebugPortType; /** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. 0x02:SOC UART2(Default). + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port + Base' options will be ignored. 0x02:SOC UART2(Default). 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device **/ uint8_t SerialDebugPortDevice; @@ -156,44 +73,63 @@ struct FSP_M_CONFIG { uint8_t MrcFastBoot; /** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video + Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ uint8_t Igd; /** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. 0x02:64 MB(Default). - 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal + Graphics Device. 0x02:64 MB(Default). + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 + MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, + 0x0F:480 MB, 0x10:512 MB **/ uint8_t IgdDvmt50PreAlloc; /** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), 0x2:256 MB, 0x3:512 MB. + Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), + 0x2:256 MB, 0x3:512 MB. 0x1:128 MB, 0x2:256 MB, 0x3:512 MB **/ uint8_t IgdApertureSize; /** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 MB(Default). + Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 + MB(Default). 0x1:2 MB, 0x2:4 MB, 0x3:8 MB **/ uint8_t GttSize; /** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), 0x2:IGD, 0x3:PCI + Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), + 0x2:IGD, 0x3:PCI 0x0:AUTO, 0x2:IGD, 0x3:PCI **/ uint8_t PrimaryVideoAdaptor; /** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. 0x00(Default). + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L + is being used. 0x00(Default). 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD **/ uint8_t Package; /** Offset 0x004E - Profile Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, + 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, + 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, + 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, + 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, + 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, + 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, + 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, + 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, + 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, + 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, + 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 **/ uint8_t Profile; @@ -204,7 +140,7 @@ struct FSP_M_CONFIG { uint8_t MemoryDown; /** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB, 0x02:2KB, 0x00(Default). + NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. 0x1:1KB, 0x2:2KB **/ uint8_t DDR3LPageSize; @@ -232,8 +168,8 @@ struct FSP_M_CONFIG { uint16_t SliceHashMask; /** Offset 0x0057 - InterleavedMode - Interleaved Mode. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS + Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. + 0x0:Disable, 0x2:Enable **/ uint8_t InterleavedMode; @@ -244,7 +180,8 @@ struct FSP_M_CONFIG { uint8_t ChannelsSlicesEnable; /** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), 0x01:Enable. + Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), + 0x01:Enable. $EN_DIS **/ uint8_t MinRefRate2xEnable; @@ -262,23 +199,30 @@ struct FSP_M_CONFIG { uint8_t RmtMode; /** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) + Memory Size Limit: This value is used to restrict the total amount of memory and + the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, + 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) **/ uint16_t MemorySizeLimit; /** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). + Low Memory Max Value: This value is used to restrict the amount of memory below + 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 + = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). **/ uint16_t LowMemoryMaxValue; /** Offset 0x0060 - DisableFastBoot - 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train of memory. + 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train + of memory. $EN_DIS **/ uint8_t DisableFastBoot; /** Offset 0x0061 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). + High Memory Max Value: This value is used to restrict the amount of memory above + 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, + 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). **/ uint16_t HighMemoryMaxValue; @@ -310,7 +254,12 @@ struct FSP_M_CONFIG { uint8_t Ch0_DramDensity; /** Offset 0x0068 - Ch0_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). 0x03(Default). + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank + Address Hashing Enable. See Address Mapping section for full description. 0:Bank + Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] + This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). + 0x03(Default). **/ uint8_t Ch0_Option; @@ -330,7 +279,11 @@ struct FSP_M_CONFIG { uint8_t Ch0_Mode2N; /** Offset 0x006C - Ch0_OdtLevels - Rank Select Interleaving Enable. See Address Mapping section for full description. 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. + [1] Bank Address Hashing Enable. See Address Mapping section for full description. + 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). **/ uint8_t Ch0_OdtLevels; @@ -352,7 +305,12 @@ struct FSP_M_CONFIG { uint8_t Ch1_DramDensity; /** Offset 0x0070 - Ch1_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B), 0x03(Default). + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB + (B), 0x03(Default). **/ uint8_t Ch1_Option; @@ -372,7 +330,8 @@ struct FSP_M_CONFIG { uint8_t Ch1_Mode2N; /** Offset 0x0074 - Ch1_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch1_OdtLevels; @@ -394,7 +353,12 @@ struct FSP_M_CONFIG { uint8_t Ch2_DramDensity; /** Offset 0x0078 - Ch2_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description.. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). 01:2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description.. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description.. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). + 01:2KB (B). **/ uint8_t Ch2_Option; @@ -414,7 +378,8 @@ struct FSP_M_CONFIG { uint8_t Ch2_Mode2N; /** Offset 0x007C - Ch2_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch2_OdtLevels; @@ -424,19 +389,26 @@ struct FSP_M_CONFIG { uint8_t Ch3_RankEnable; /** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), 0x01:x16, 0x02:x32, 0x03:x64. + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), + 0x01:x16, 0x02:x32, 0x03:x64. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ uint8_t Ch3_DeviceWidth; /** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), + 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ uint8_t Ch3_DramDensity; /** Offset 0x0080 - Ch3_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] Bank Address Hashing Enable. See Address Mapping section for full description.. 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - 2KB (B). + Rank Select Interleaving Enable. See Address Mapping section for full description.. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description.. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 + - 2KB (B). **/ uint8_t Ch3_Option; @@ -456,7 +428,8 @@ struct FSP_M_CONFIG { uint8_t Ch3_Mode2N; /** Offset 0x0084 - Ch3_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ uint8_t Ch3_OdtLevels; @@ -495,25 +468,65 @@ struct FSP_M_CONFIG { **/ uint32_t MsgLevelMask; -/** Offset 0x010C - FIT Table Pointer - FIT table pointer. 0x00000000(Default). +/** Offset 0x010C +**/ + uint32_t UnusedUpdSpace0; + +/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 + Number of Entries in PreMem GPIO Table. 0(Default). **/ - uint32_t FitTablePtr; + uint8_t PreMemGpioTableEntryNum; -/** Offset 0x0110 - GPIO Table Pointer - GPIO table pointer to a BL_GPIO_PAD_INIT structure. 0x00000000(Default). +/** Offset 0x0111 - PreMem GPIO Pin Number for each table + Number of Pins in each PreMem GPIO Table. 0(Default). **/ - struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; + uint8_t PreMemGpioTablePinNum[4]; -/** Offset 0x0114 - Enhance the port 8xh decoding +/** Offset 0x0115 - PreMem GPIO Table Pointer + Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). +**/ + uint32_t PreMemGpioTablePtr; + +/** Offset 0x0119 - Enhance the port 8xh decoding Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t EnhancePort8xhDecoding; -/** Offset 0x0115 +/** Offset 0x011A - OEM File Loading Address + Determine the memory base address to load a specified file from CSE file system + after memory is available. +**/ + uint32_t OemLoadingBase; + +/** Offset 0x011E - OEM File Name to Load + Specify a file name to load from CSE file system after memory is available. Empty + indicates no file needs to be loaded. +**/ + uint8_t OemFileName[16]; + +/** Offset 0x012E - SPD Data Write + Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SpdWriteEnable; + +/** Offset 0x012F - MRC Training Data Saving + Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t MrcDataSaving; + +/** Offset 0x0130 - eMMC Trace Length + Select eMMC trace length to load OEM file from when loading OEM file name is specified. + 0x0:Long(Default), 0x1:Short. + 0x0:Long, 0x1:Short **/ - uint8_t ReservedFspmUpd[59]; + uint8_t eMMCTraceLen; + +/** Offset 0x0131 +**/ + uint8_t ReservedFspmUpd[31]; } __attribute__((packed)); /** Fsp M Test Configuration @@ -542,8 +555,6 @@ struct FSP_M_RESTRICTED_CONFIG { uint8_t ReservedFspmRestrictedUpd[138]; } __attribute__((packed)); -#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ - /** Fsp M UPD Configuration **/ struct FSPM_UPD { @@ -554,7 +565,7 @@ struct FSPM_UPD { /** Offset 0x0020 **/ - struct FSP_M_ARCH_UPD FspmArchUpd; + struct FSPM_ARCH_UPD FspmArchUpd; /** Offset 0x0040 **/ diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index 2ada27f806..92c2d752bc 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -34,7 +34,7 @@ are permitted provided that the following conditions are met: #define __FSPSUPD_H__ #include "FspUpd.h" - +#include <fsp/upd.h> /** Fsp S Configuration **/ @@ -70,7 +70,8 @@ struct FSP_S_CONFIG { uint8_t VmxEnable; /** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default) + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to + 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default) **/ uint8_t ProcTraceMemSize; @@ -110,7 +111,8 @@ struct FSP_S_CONFIG { uint8_t BiProcHot; /** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. + Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, + 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. **/ uint8_t PkgCStateLimit; @@ -119,12 +121,15 @@ struct FSP_S_CONFIG { uint8_t UnusedUpdSpace0; /** Offset 0x002E - C-State auto-demotion - C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion to C1 and C3. + C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 + Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion + to C1 and C3. **/ uint8_t CStateAutoDemotion; /** Offset 0x002F - C-State un-demotion - C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. + C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, + 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. **/ uint8_t CStateUnDemotion; @@ -436,7 +441,8 @@ struct FSP_S_CONFIG { /** Offset 0x0091 - HD-Audio I/O Buffer Ownership Set HD-Audio I/O Buffer Ownership. 0:Disable(Default), 1:Enable. - 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and + I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers **/ uint8_t HdAudioIoBufferOwnership; @@ -453,13 +459,15 @@ struct FSP_S_CONFIG { uint8_t HdAudioVcType; /** Offset 0x0094 - HD-Audio Link Frequency - HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. + HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid **/ uint8_t HdAudioLinkFrequency; /** Offset 0x0095 - HD-Audio iDisp-Link Frequency - HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. + HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid **/ uint8_t HdAudioIDispLinkFrequency; @@ -495,13 +503,13 @@ struct FSP_S_CONFIG { uint8_t DspEndpointI2sHp; /** Offset 0x009B - HD-Audio Controller Power Gating - Enable/Disable HD-Audio Controller Power Gating. 0:Disable(Default), 1:Enable. + Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. $EN_DIS **/ uint8_t AudioCtlPwrGate; /** Offset 0x009C - HD-Audio ADSP Power Gating - Enable/Disable HD-Audio ADSP Power Gating. 0:Disable(Default), 1:Enable. + Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. $EN_DIS **/ uint8_t AudioDspPwrGate; @@ -538,13 +546,17 @@ struct FSP_S_CONFIG { /** Offset 0x00A2 - Bitmask of DSP Feature Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation **/ uint32_t DspFeatureMask; /** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation **/ uint32_t DspPpModuleMask; @@ -624,7 +636,8 @@ struct FSP_S_CONFIG { uint8_t IshEnable; /** Offset 0x00BB - ISH Controller - Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). + Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control + Register. 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t BiosInterface; @@ -768,11 +781,11 @@ struct FSP_S_CONFIG { **/ uint8_t OsDbgEnable; -/** Offset 0x00E3 - Exi Feature - Enable/Disable Exi Feature. 0:Disable(Default), 1: Enable. +/** Offset 0x00E3 - DCI Feature + Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. $EN_DIS **/ - uint8_t ExiEnable; + uint8_t DciEn; /** Offset 0x00E4 - Enable PCIE Clock Gating Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). @@ -848,7 +861,8 @@ struct FSP_S_CONFIG { uint8_t PcieRpClkReqSupported[6]; /** Offset 0x011F - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, 0x01, 0x02, 0x03. + Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, + 0x01, 0x02, 0x03. **/ uint8_t PcieRpClkReqNumber[6]; @@ -923,7 +937,8 @@ struct FSP_S_CONFIG { uint8_t PtmEnable[6]; /** Offset 0x0179 - ASPM - PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, 4:Auto(Default). + PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, + 4:Auto(Default). **/ uint8_t PcieRpAspm[6]; @@ -949,19 +964,21 @@ struct FSP_S_CONFIG { uint8_t PmeB0S5Dis; /** Offset 0x0192 - PCI Clock Run - This member describes whether or not the PCI ClockRun feature of SC should be enabled. 0:Disable(Default), 1:Enable. + This member describes whether or not the PCI ClockRun feature of SC should be enabled. + 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t PciClockRun; /** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock. 0:Disable, 1:Enable(Default). + Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. $EN_DIS **/ uint8_t Timer8254ClkSetting; /** Offset 0x0194 - Chipset SATA - Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). + Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports + the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). $EN_DIS **/ uint8_t EnableSata; @@ -1012,7 +1029,8 @@ struct FSP_S_CONFIG { uint8_t SataPortsHotPlug[2]; /** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires hardware support. 0:Disable, 1:Enable(Default). + Controls reporting if this port has an Mechanical Presence Switch.\nNote:Requires + hardware support. 0:Disable, 1:Enable(Default). **/ uint8_t SataPortsInterlockSw[2]; @@ -1027,7 +1045,8 @@ struct FSP_S_CONFIG { uint8_t SataPortsSpinUp[2]; /** Offset 0x01A6 - SATA Solid State - Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard Disk Drive(Default), 1:Solid State Drive. + Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard + Disk Drive(Default), 1:Solid State Drive. **/ uint8_t SataPortsSolidStateDrive[2]; @@ -1163,7 +1182,8 @@ struct FSP_S_CONFIG { uint8_t RsvdSmbusAddressTable[128]; /** Offset 0x024F - XHCI Disable Compliance Mode - Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. + Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance + Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. $EN_DIS **/ uint8_t DisableComplianceMode; @@ -1181,7 +1201,8 @@ struct FSP_S_CONFIG { uint8_t Usb30Mode; /** Offset 0x0252 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). **/ uint8_t PortUsb20Enable[8]; @@ -1191,7 +1212,8 @@ struct FSP_S_CONFIG { uint8_t PortUs20bOverCurrentPin[8]; /** Offset 0x0262 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). **/ uint8_t PortUsb30Enable[6]; @@ -1213,7 +1235,8 @@ struct FSP_S_CONFIG { uint8_t HsicSupportEnable; /** Offset 0x0270 - Enable XHCI SSIC Support - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. 0x00(Default). + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for + port1. 0x00(Default). **/ uint8_t SsicPortEnable[2]; @@ -1235,7 +1258,8 @@ struct FSP_S_CONFIG { uint16_t ResetWaitTimer; /** Offset 0x0277 - SMI Lock bit - Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, 1:Enable(Default). + Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, + 1:Enable(Default). $EN_DIS **/ uint8_t LockDownGlobalSmi; @@ -1269,7 +1293,8 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxSnoopLatency[6]; /** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). + Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually + enter override values.\nAuto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ uint8_t PcieRpSnoopLatencyOverrideMode[6]; @@ -1279,7 +1304,8 @@ struct FSP_S_CONFIG { uint16_t PcieRpSnoopLatencyOverrideValue[6]; /** Offset 0x029C - Snoop Latency Multiplier - LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. + LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, + 4:1048576ns, 5:33554432ns. **/ uint8_t PcieRpSnoopLatencyOverrideMultiplier[6]; @@ -1289,7 +1315,9 @@ struct FSP_S_CONFIG { uint16_t PcieRpLtrMaxNonSnoopLatency[6]; /** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). + Non Snoop Latency Override for PCH PCIE. \nDisabled:Disable override.\nManual:Manually + enter override values.\nAuto: Maintain default BIOS flow. 0:Disable, 1:Enable, + 2:Auto(Default). **/ uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; @@ -1299,7 +1327,8 @@ struct FSP_S_CONFIG { uint16_t PcieRpNonSnoopLatencyOverrideValue[6]; /** Offset 0x02C0 - Non Snoop Latency Multiplier - LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. + LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), + 3:32768ns, 4:1048576ns, 5:33554432ns. **/ uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6]; @@ -1314,25 +1343,154 @@ struct FSP_S_CONFIG { uint8_t PcieRpSlotPowerLimitValue[6]; /** Offset 0x02D2 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize(Default), <b>1: Skip + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize(Default), <b>1: Skip $EN_DIS **/ uint8_t SkipMpInit; -/** Offset 0x02D3 +/** Offset 0x02D3 - DCI Auto Detect + Enable/disable DCI AUTO mode. + $EN_DIS +**/ + uint8_t DciAutoDetect; + +/** Offset 0x02D4 - Halt and Lock TCO Timer + Halt and Lock the TCO Timer (Watchdog). + 0:No, 1:Yes (default) +**/ + uint8_t TcoTimerHaltLock; + +/** Offset 0x02D5 - Power Button Override Peroid + specifies how long will PMC wait before initiating a global reset. 000b-4s(default), + 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) + 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s +**/ + uint8_t PwrBtnOverridePeriod; + +/** Offset 0x02D6 - Power Button Native Mode Disable + Diable power button native mode, when 1, this will result in the PMC logic constantly + seeing the power button as de-asserted. 0 (default)) + $EN_DIS +**/ + uint8_t DisableNativePowerButton; + +/** Offset 0x02D7 - Power Button Debounce Mode + Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) + $EN_DIS +**/ + uint8_t PowerButterDebounceMode; + +/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL + SDIO_TX_CMD_DLL_CNTL. 0x505(Default). **/ - uint8_t ReservedFspsUpd[45]; + uint32_t SdioTxCmdCntl; + +/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 + SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). +**/ + uint32_t SdioTxDataCntl1; + +/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 + SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). +**/ + uint32_t SdioTxDataCntl2; + +/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 + SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). +**/ + uint32_t SdioRxCmdDataCntl1; + +/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 + SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + uint32_t SdioRxCmdDataCntl2; + +/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL + SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + uint32_t SdcardTxCmdCntl; + +/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 + SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). +**/ + uint32_t SdcardTxDataCntl1; + +/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 + SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). +**/ + uint32_t SdcardTxDataCntl2; + +/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 + SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). +**/ + uint32_t SdcardRxCmdDataCntl1; + +/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL + SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). +**/ + uint32_t SdcardRxStrobeCntl; + +/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 + SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + uint32_t SdcardRxCmdDataCntl2; + +/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL + EMMC_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + uint32_t EmmcTxCmdCntl; + +/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 + EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). +**/ + uint32_t EmmcTxDataCntl1; + +/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 + EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). +**/ + uint32_t EmmcTxDataCntl2; + +/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 + EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). +**/ + uint32_t EmmcRxCmdDataCntl1; + +/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL + EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). +**/ + uint32_t EmmcRxStrobeCntl; + +/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 + EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). +**/ + uint32_t EmmcRxCmdDataCntl2; + +/** Offset 0x031C - EMMC_MASTER_DLL_CNTL + EMMC_MASTER_DLL_CNTL. 0x001(Default). +**/ + uint32_t EmmcMasterSwCntl; + +/** Offset 0x0320 - PCIe Selectable De-emphasis + When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis + for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpSelectableDeemphasis[6]; + +/** Offset 0x0326 +**/ + uint8_t ReservedFspsUpd[10]; } __attribute__((packed)); /** Fsp S Test Configuration **/ struct FSP_S_TEST_CONFIG { -/** Offset 0x0300 +/** Offset 0x0330 **/ uint32_t Signature; -/** Offset 0x0304 +/** Offset 0x0334 **/ uint8_t ReservedFspsTestUpd[12]; } __attribute__((packed)); @@ -1341,17 +1499,15 @@ struct FSP_S_TEST_CONFIG { **/ struct FSP_S_RESTRICTED_CONFIG { -/** Offset 0x0310 +/** Offset 0x0340 **/ uint32_t Signature; -/** Offset 0x0314 +/** Offset 0x0344 **/ uint8_t ReservedFspsRestrictedUpd[12]; } __attribute__((packed)); -#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ - /** Fsp S UPD Configuration **/ struct FSPS_UPD { @@ -1364,15 +1520,15 @@ struct FSPS_UPD { **/ struct FSP_S_CONFIG FspsConfig; -/** Offset 0x0300 +/** Offset 0x0330 **/ struct FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0310 +/** Offset 0x0340 **/ struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; -/** Offset 0x0320 +/** Offset 0x0350 **/ uint16_t UpdTerminator; } __attribute__((packed)); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 434d11fa20..dec5a18601 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -218,7 +218,7 @@ static void fill_console_params(struct FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; - struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; struct chipset_power_state *ps = car_get_var_ptr(&power_state); int prev_sleep_state = chipset_prev_sleep_state(ps); @@ -226,12 +226,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) mainboard_memory_init_params(mupd); /* Do NOT let FSP do any GPIO pad configuration */ - mupd->FspmConfig.GpioPadInitTablePtr = NULL; - /* - * At FIT_POINTER there is an address that points to FIT. Even though it - * is technically 64bit value we know only 32bit address is used. - */ - mupd->FspmConfig.FitTablePtr = read32((void*) FIT_POINTER); + mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; /* Reserve enough memory under TOLUD to save CBMEM header */ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); /* @@ -247,18 +242,18 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; #endif - arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; + arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = + arch_upd->BootMode = prev_sleep_state == SLEEP_STATE_S3 ? FSP_BOOT_ON_S3_RESUME: FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", - mrc_cache->size, arch_upd->Bootmode); + mrc_cache->size, arch_upd->BootMode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); } |