diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 7 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/nvs.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/acpi/sgx.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/globalnvs.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/nvs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/sgx.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sgx/sgx.c | 55 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 4 |
10 files changed, 45 insertions, 50 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4f5029e5ac..0e60771207 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -12,7 +12,6 @@ #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/pmclib.h> -#include <intelblocks/sgx.h> #include <intelblocks/p2sb.h> #include <soc/iomap.h> #include <soc/pm.h> @@ -88,9 +87,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); } - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - sgx_fill_gnvs(gnvs); - /* Fill in Above 4GB MMIO resource */ sa_fill_gnvs(gnvs); } diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 225e9db7ea..41f2409990 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -23,9 +23,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) SCDP, 8, // 0x29 - SD_CD GPIO portid SCDO, 8, // 0x2A - GPIO pad offset relative to the community UIOR, 8, // 0x2B - UART debug controller init on S3 resume - EPCS, 8, // 0x2C - SGX Enabled status - EMNA, 64, // 0x2D - 0x34 EPC base address - ELNG, 64, // 0x35 - 0x3C EPC Length - A4GB, 64, // 0x3D - 0x44 Base of above 4GB MMIO Resource - A4GS, 64, // 0x45 - 0x4C Length of above 4GB MMIO Resource + A4GB, 64, // 0x2C - 0x33 Base of above 4GB MMIO Resource + A4GS, 64, // 0x34 - 0x3B Length of above 4GB MMIO Resource } diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index b471748653..a9e02306fb 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,11 +28,8 @@ struct __packed global_nvs { uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */ uint8_t uior; /* 0x2B - UART debug controller init on S3 resume */ - uint8_t epcs; /* 0x2C - SGX Enabled status */ - uint64_t emna; /* 0x2D - 0x34 EPC base address */ - uint64_t elng; /* 0x35 - 0x3C EPC Length */ - uint64_t a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */ - uint64_t a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */ + uint64_t a4gb; /* 0x2C - 0x33 Base of above 4GB MMIO Resource */ + uint64_t a4gs; /* 0x34 - 0x3B Length of above 4GB MMIO Resource */ }; #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index 9aea7a8b09..cfd7f7ed2a 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -6,6 +6,9 @@ Scope(\_SB) // Secure Enclave memory Device (EPC) { + External (EPCS, IntObj) + External (EMNA, IntObj) + External (ELNG, IntObj) Name (_HID, EISAID ("INT0E0C")) Name (_STR, Unicode ("Enclave Page Cache 1.0")) Name (_MLS, Package () { diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 16017779d9..b827c58bc1 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -15,6 +15,7 @@ #include <intelblocks/acpi_wake_source.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> +#include <intelblocks/sgx.h> #include <intelblocks/uart.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -427,4 +428,7 @@ void generate_cpu_entries(const struct device *device) /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(num_virt); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) + sgx_fill_ssdt(); } diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 003a5ce3df..ab63a5c407 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -25,7 +25,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve) A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource , 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code) - EPCS, 8, // 0x48 - SGX enabled status - EMNA, 64, // 0x49 - 0x50 EPC base address - ELNG, 64, // 0x51 - 0x58 EPC length } diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 3ebb08b519..5adbdb8550 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -27,10 +27,6 @@ struct __packed global_nvs { u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ u64 hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */ - /* SGX */ - u8 epcs; /* 0x48 - SGX enabled status */ - u64 emna; /* 0x49 - 0x50 EPC base address */ - u64 elng; /* 0x51 - 0x58 EPC length */ }; #endif diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 56e4a167b5..fc7282f011 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -17,7 +17,7 @@ void prmrr_core_configure(void); */ void sgx_configure(void *unused); -/* Fill GNVS data with SGX status, EPC base and length */ -void sgx_fill_gnvs(struct global_nvs *gnvs); +/* Fill SSDT for SGX status, EPC base and length */ +void sgx_fill_ssdt(void); #endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index e0dcd85861..d15fc0f049 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -10,7 +11,6 @@ #include <intelblocks/sgx.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> static inline uint64_t sgx_resource(uint32_t low, uint32_t high) @@ -235,31 +235,40 @@ void sgx_configure(void *unused) activate_sgx(); } -void sgx_fill_gnvs(struct global_nvs *gnvs) +void sgx_fill_ssdt(void) { + bool epcs = false; struct cpuid_result cpuid_regs; - - if (!is_sgx_supported()) { - printk(BIOS_DEBUG, - "SGX: not supported. skip gnvs fill\n"); - return; + uint64_t emna = 0, elng = 0; + + if (is_sgx_supported()) { + /* + * Get EPC base and size. + * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or + * Higher for enumeration of SGX Resources. Same Table mentions + * about return values of the CPUID + */ + cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, + SGX_RESOURCE_ENUM_CPUID_SUBLEAF); + + if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { + /* EPC section enumerated */ + epcs = true; + emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); + elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); + } + + printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n", + epcs, emna, elng); + } else { + printk(BIOS_DEBUG, "SGX: not supported.\n"); } - /* Get EPC base and size. - * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or - * Higher for enumeration of SGX Resources. Same Table mentions - * about return values of the CPUID */ - cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, - SGX_RESOURCE_ENUM_CPUID_SUBLEAF); - - if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { - /* EPC section enumerated */ - gnvs->epcs = 1; - gnvs->emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); - gnvs->elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); + acpigen_write_scope("\\_SB.EPC"); + { + acpigen_write_name_byte("EPCS", epcs); + acpigen_write_name_qword("EMNA", emna); + acpigen_write_name_qword("ELNG", elng); } - - printk(BIOS_DEBUG, - "SGX: gnvs EPC status = %d base = 0x%llx len = 0x%llx\n", - gnvs->epcs, gnvs->emna, gnvs->elng); + acpigen_pop_len(); } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 4794a998f9..fc2b65d165 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -13,7 +13,6 @@ #include <intelblocks/acpi_wake_source.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/sgx.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pm.h> @@ -179,9 +178,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - sgx_fill_gnvs(gnvs); - /* Fill in Above 4GB MMIO resource */ sa_fill_gnvs(gnvs); } |