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-rw-r--r--src/soc/intel/alderlake/Kconfig7
-rw-r--r--src/soc/intel/common/block/acpi/Kconfig7
-rw-r--r--src/soc/intel/common/block/acpi/acpi/ufs.asl4
3 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 92a8c06840..fe7b3a229b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -425,6 +425,13 @@ config ACPI_ADL_IPU_ES_SUPPORT
help
Enables ACPI entry to provide silicon type information to IPU kernel driver.
+config ALDERLAKE_ENABLE_SOC_WORKAROUND
+ bool
+ default y
+ select SOC_INTEL_UFS_OCP_TIMER_DISABLE
+ help
+ Selects the workarounds applicable for Alder Lake SoC.
+
choice
prompt "Multiprocessor (MP) Initialization configuration to use"
default USE_FSP_MP_INIT
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig
index e21584c073..2b102bca42 100644
--- a/src/soc/intel/common/block/acpi/Kconfig
+++ b/src/soc/intel/common/block/acpi/Kconfig
@@ -49,4 +49,11 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
help
Defines hybrid CPU specific ACPI helper functions.
+config SOC_INTEL_UFS_OCP_TIMER_DISABLE
+ bool
+ help
+ OCP Timer need to be disabled in SCS UFS IOSF Bridge to
+ work around the Silicon Issue due to which LTR mechanism
+ doesn't work.
+
endif
diff --git a/src/soc/intel/common/block/acpi/acpi/ufs.asl b/src/soc/intel/common/block/acpi/acpi/ufs.asl
index 41c14d7863..f7cb9f336e 100644
--- a/src/soc/intel/common/block/acpi/acpi/ufs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/ufs.asl
@@ -67,8 +67,10 @@ Scope (\_SB.PCI0)
/* Set BIT[1:0] = 00b - Power State D0 */
PSTA &= 0xFFFFFFFC
+#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
/* Disable OCP Timer in SCS UFS IOSF Bridge */
OCPD ()
+#endif
}
Method (_PS3, 0, Serialized)
@@ -79,7 +81,9 @@ Scope (\_SB.PCI0)
Method (_INI)
{
+#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
OCPD ()
+#endif
}
}
}