diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 23 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mp_init.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 4 |
4 files changed, 13 insertions, 26 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f81c2eef8d..98cd23ade4 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -60,7 +60,7 @@ static const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void soc_core_init(device_t cpu, const void *microcode) +void soc_core_init(device_t cpu) { /* Set core MSRs */ reg_script_run(core_msr_script); @@ -75,7 +75,7 @@ void soc_core_init(device_t cpu, const void *microcode) #if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) static void soc_init_core(device_t cpu) { - soc_core_init(cpu, NULL); + soc_core_init(cpu); } static struct device_operations cpu_dev_ops = { @@ -223,7 +223,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = smm_southbridge_enable, }; -void soc_init_cpus(struct bus *cpu_bus, const void *microcode) +void soc_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops)) @@ -234,7 +234,7 @@ void apollolake_init_cpus(struct device *dev) { if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) return; - soc_init_cpus(dev->link_list, NULL); + soc_init_cpus(dev->link_list); /* Temporarily cache the memory-mapped boot media. */ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 5bbbb2c01e..c08d251469 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -30,20 +30,19 @@ static const void *microcode_patch; /* SoC override function */ -__attribute__((weak)) void soc_core_init(device_t dev, const void *microcode) +__attribute__((weak)) void soc_core_init(device_t dev) { /* no-op */ } -__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus, - const void *microcode) +__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus) { /* no-op */ } -static void init_one_cpu(device_t dev) +static void init_one_cpu(device_t dev) { - soc_core_init(dev, microcode_patch); + soc_core_init(dev); intel_microcode_load_unlocked(microcode_patch); } @@ -125,19 +124,7 @@ static void init_cpus(void *unused) microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); - /* - * TODO: This parameter "microcode_patch" should be removed - * in this function call once the following two cases are resolved - - * - * 1) SGX enabling for the BSP issue gets solved, due to which - * configure_sgx() function is kept inside soc/cpu.c soc_init_cpus(). - * 2) uCode loading after SMM relocation is deleted inside - * per_cpu_smm_trigger() mp_ops callback function in soc/cpu.c, - * since as per current BWG, uCode loading can be done after - * all feature programmings are done. There is no specific - * recommendation to do it after SMM Relocation. - */ - soc_init_cpus(dev->link_list, microcode_patch); + soc_init_cpus(dev->link_list); } /* Ensure to re-program all MTRRs based on DRAM resource settings */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index d123207c58..640be76a91 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -70,7 +70,7 @@ void get_microcode_info(const void **microcode, int *parallel); * In this function SOC must perform CPU feature programming * during Ramstage phase. */ -void soc_core_init(device_t dev, const void *microcode); +void soc_core_init(device_t dev); /* * In this function SOC must fill required mp_ops params, also it @@ -80,6 +80,6 @@ void soc_core_init(device_t dev, const void *microcode); * Also, if there is any other SOC specific functionalities to be * implemented before or after MP Init, it can be done here. */ -void soc_init_cpus(struct bus *cpu_bus, const void *microcode); +void soc_init_cpus(struct bus *cpu_bus); #endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index fe9c00841d..a7745cec91 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -407,7 +407,7 @@ static void enable_pm_timer_emulation(void) } /* All CPUs including BSP will run the following function. */ -void soc_core_init(device_t cpu, const void *microcode) +void soc_core_init(device_t cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -491,7 +491,7 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void soc_init_cpus(struct bus *cpu_bus, const void *microcode) +void soc_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); |