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-rw-r--r--src/soc/intel/cannonlake/cpu.c3
-rw-r--r--src/soc/intel/icelake/cpu.c3
-rw-r--r--src/soc/intel/skylake/cpu.c9
-rw-r--r--src/soc/intel/tigerlake/cpu.c3
4 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index f01b499108..3ba0562980 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -263,9 +263,10 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+
/* Set EIST status */
cpu_set_eist(conf->eist_enable);
- wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
msr.lo = 0;
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index e058442585..91282d8a66 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -71,9 +71,10 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+
/* Set EIST status */
cpu_set_eist(conf->eist_enable);
- wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
msr.lo = 0;
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index f5273f6fc7..d7da56eaf7 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -291,14 +291,11 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
-
- if (conf->eist_enable)
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
- else
- msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
-
wrmsr(IA32_MISC_ENABLE, msr);
+ /* Set EIST status */
+ cpu_set_eist(conf->eist_enable);
+
/* Disable Thermal interrupts */
msr.lo = 0;
msr.hi = 0;
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 5f4f081818..cfbfdb3ea4 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -77,9 +77,10 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+
/* Set EIST status */
cpu_set_eist(conf->eist_enable);
- wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
msr.lo = 0;