diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fb0d8278b8..59651d58b3 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -248,6 +248,8 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* Implemented as slot or built-in? */ + uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index f04c3d7b5a..1cf3d2fee8 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -402,6 +402,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; params->PciePtm[i] = config->PciePtm[i]; + params->PcieRpSlotImplemented[i] = config->PcieRpSlotImplemented[i]; } /* Enable ClkReqDetect for enabled port */ |