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-rw-r--r--src/soc/intel/broadwell/include/soc/romstage.h4
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c5
2 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index 31184f9a02..46f29d62df 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -18,13 +18,13 @@
#include <stdint.h>
#include <arch/cpu.h>
+#include <soc/pei_data.h>
struct chipset_power_state;
-struct pei_data;
struct romstage_params {
unsigned long bist;
struct chipset_power_state *power_state;
- struct pei_data *pei_data;
+ struct pei_data pei_data;
};
void mainboard_romstage_entry(struct romstage_params *params);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 7847829ac6..2a3ac8b8e6 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -68,7 +68,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
{
struct romstage_params rp = {
.bist = bist,
- .pei_data = NULL,
};
post_code(0x30);
@@ -125,7 +124,7 @@ void romstage_common(struct romstage_params *params)
timestamp_add_now(TS_BEFORE_INITRAM);
- params->pei_data->boot_mode = params->power_state->prev_sleep_state;
+ params->pei_data.boot_mode = params->power_state->prev_sleep_state;
#if CONFIG(ELOG_BOOT_COUNT)
if (params->power_state->prev_sleep_state != ACPI_S3)
@@ -140,7 +139,7 @@ void romstage_common(struct romstage_params *params)
&params->power_state->hsio_checksum);
/* Initialize RAM */
- raminit(params->pei_data);
+ raminit(&params->pei_data);
timestamp_add_now(TS_AFTER_INITRAM);