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-rw-r--r--src/soc/intel/alderlake/meminit.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 8b5e0071ef..cbc2b5ccfb 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -62,18 +62,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
.num_phys_channels = DDR5_CHANNELS,
.phys_to_mrc_map = {
[0] = 0,
- [1] = 1,
- [2] = 4,
- [3] = 5,
+ [1] = 4,
},
.md_phy_masks = {
/*
- * Physical channels 0 and 1 are populated in case of
- * half-populated configurations.
+ * Only channel 0 is populated in case of half-populated
+ * configuration.
*/
- .half_channel = BIT(0) | BIT(1),
- /* In mixed topologies, channels 2 and 3 are always memory-down. */
- .mixed_topo = BIT(2) | BIT(3),
+ .half_channel = BIT(0),
+ /* In mixed topologies, channel 1 is always memory-down. */
+ .mixed_topo = BIT(1),
},
},
[MEM_TYPE_LP4X] = {