diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index cfd04760fa..597f8c5d5b 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -80,13 +80,13 @@ * + +-----------+-------+-------+---------+-------------+----------+ * | | GT | 3.2 | 3.2 | 55 | 86 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ - * | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 54 | 28000 | + * | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 33 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ - * | | GT | 3.2 | 3.2 | 55 | 54 | 28000 | + * | | GT | 3.2 | 3.2 | 55 | 33 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ - * | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 41 | 28000 | + * | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 22 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ - * | | GT | 3.2 | 3.2 | 40 | 41 | 28000 | + * | | GT | 3.2 | 3.2 | 40 | 22 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ */ @@ -245,10 +245,10 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, - { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) }, - { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, - { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, - { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, |