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-rw-r--r--src/soc/intel/skylake/Kconfig9
-rw-r--r--src/soc/intel/skylake/igd.c10
2 files changed, 0 insertions, 19 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index c558886584..af1381af7d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -169,15 +169,6 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
-config PRE_GRAPHICS_DELAY
- int "Graphics initialization delay in ms"
- default 0
- help
- On some systems, coreboot boots so fast that connected monitors
- (mostly TVs) won't be able to wake up fast enough to talk to the
- VBIOS. On those systems we need to wait for a bit before executing
- the VBIOS.
-
config SERIAL_CPU_INIT
bool
default n
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 9304f6fe10..3f35489262 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -93,16 +93,6 @@ static void igd_init(struct device *dev)
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
- /* Wait for any configured pre-graphics delay */
- if (!acpi_is_wakeup_s3()) {
-#if IS_ENABLED(CONFIG_CHROMEOS)
- if (display_init_required() || vboot_wants_oprom())
- mdelay(CONFIG_PRE_GRAPHICS_DELAY);
-#else
- mdelay(CONFIG_PRE_GRAPHICS_DELAY);
-#endif
- }
-
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
}