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-rw-r--r--src/soc/intel/tigerlake/include/soc/pm.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/pmc.h4
-rw-r--r--src/soc/intel/tigerlake/pmutil.c3
3 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h
index c42e280ed1..c69fe3edb8 100644
--- a/src/soc/intel/tigerlake/include/soc/pm.h
+++ b/src/soc/intel/tigerlake/include/soc/pm.h
@@ -150,6 +150,7 @@ struct chipset_power_state {
uint32_t gen_pmcon_a;
uint32_t gen_pmcon_b;
uint32_t gblrst_cause[2];
+ uint32_t hpr_cause0;
uint32_t prev_sleep_state;
} __packed;
diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h
index 88c6f61d94..9ad3391348 100644
--- a/src/soc/intel/tigerlake/include/soc/pmc.h
+++ b/src/soc/intel/tigerlake/include/soc/pmc.h
@@ -119,6 +119,10 @@
#define GBLRST_CAUSE0 0x1924
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
#define GBLRST_CAUSE1 0x1928
+#define HPR_CAUSE0 0x192C
+#define HPR_CAUSE0_MI_HRPD (1 << 10)
+#define HPR_CAUSE0_MI_HRPC (1 << 9)
+#define HPR_CAUSE0_MI_HR (1 << 8)
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 4482b1ec55..554932bd72 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -260,12 +260,15 @@ void soc_fill_power_state(struct chipset_power_state *ps)
ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+ ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
ps->gen_pmcon_a, ps->gen_pmcon_b);
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
ps->gblrst_cause[0], ps->gblrst_cause[1]);
+
+ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
}
/* STM Support */