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-rw-r--r--src/soc/intel/alderlake/bootblock/pch.c18
-rw-r--r--src/soc/intel/alderlake/espi.c9
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c18
-rw-r--r--src/soc/intel/cannonlake/lpc.c23
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpc_lib.h5
-rw-r--r--src/soc/intel/common/block/lpc/lpc_lib.c1
-rw-r--r--src/soc/intel/common/pch/Kconfig1
-rw-r--r--src/soc/intel/elkhartlake/bootblock/pch.c18
-rw-r--r--src/soc/intel/elkhartlake/espi.c24
-rw-r--r--src/soc/intel/icelake/bootblock/pch.c18
-rw-r--r--src/soc/intel/icelake/espi.c24
-rw-r--r--src/soc/intel/jasperlake/bootblock/pch.c18
-rw-r--r--src/soc/intel/jasperlake/espi.c24
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c17
-rw-r--r--src/soc/intel/skylake/lpc.c10
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c18
-rw-r--r--src/soc/intel/tigerlake/espi.c24
-rw-r--r--src/soc/intel/xeon_sp/Kconfig2
-rw-r--r--src/soc/intel/xeon_sp/lpc.c10
19 files changed, 17 insertions, 265 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index 528e4de46e..662f33e1b7 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -40,9 +40,6 @@
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static void soc_config_pwrmbase(void)
{
/*
@@ -123,19 +120,8 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in ESPI PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
index b489ef6a15..feec465a92 100644
--- a/src/soc/intel/alderlake/espi.c
+++ b/src/soc/intel/alderlake/espi.c
@@ -30,15 +30,6 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
#if ENV_RAMSTAGE
void lpc_soc_init(struct device *dev)
{
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index f4208450b3..a618988116 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -38,9 +38,6 @@
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static uint32_t get_pmc_reg_base(void)
{
if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
@@ -140,19 +137,8 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in LPC PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index b03f21e2a2..20704e5bc6 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -9,7 +9,6 @@
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/lpc.h>
@@ -28,28 +27,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
#if ENV_RAMSTAGE
-static void soc_mirror_dmi_pcr_io_dec(void)
-{
- uint32_t io_dec_arr[] = {
- pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),
- pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),
- pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),
- pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),
- };
- /* Mirror these same settings in DMI PCR */
- soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
-}
-
void lpc_soc_init(struct device *dev)
{
const config_t *config = dev->chip_info;
@@ -69,7 +47,6 @@ void lpc_soc_init(struct device *dev)
pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
- soc_mirror_dmi_pcr_io_dec();
}
/* Fill up LPC IO resource structure inside SoC directory */
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index c5842d5f2c..c22eea3ad0 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -26,9 +26,6 @@
#define LPC_NUM_GENERIC_IO_RANGES 4
#define PCR_DMI_LPCLGIR1 0x2730
-#define PCR_DMI_LPCLGIR2 0x2734
-#define PCR_DMI_LPCLGIR3 0x2738
-#define PCR_DMI_LPCLGIR4 0x273c
#define PCR_DMI_LPCGMR 0x2740
@@ -88,8 +85,6 @@ void lpc_io_setup_comm_a_b(void);
void pch_enable_lpc(void);
/* Get SoC's generic IO decoder range register settings. */
void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
-/* Mirror generic IO decoder range register settings into DMI PCR. */
-void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
/* Add resource into LPC PCI device space */
void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
uintptr_t base, size_t size, unsigned long flags);
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 242d7d91c9..73a472799f 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -258,7 +258,6 @@ void pch_enable_lpc(void)
soc_get_gen_io_dec_range(gen_io_dec);
lpc_set_gen_decode_range(gen_io_dec);
- soc_setup_dmi_pcr_io_dec(gen_io_dec);
if (ENV_PAYLOAD_LOADER)
pch_pirq_init();
}
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index b00fc8bb71..644fed1f4d 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -27,6 +27,7 @@ config PCH_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPC
+ select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PCIE
diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index e1414f11fe..288589ae90 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -37,9 +37,6 @@
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static void soc_config_pwrmbase(void)
{
/*
@@ -121,19 +118,8 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in ESPI PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
index f33eca52c6..1737a474ac 100644
--- a/src/soc/intel/elkhartlake/espi.c
+++ b/src/soc/intel/elkhartlake/espi.c
@@ -7,7 +7,6 @@
#include <device/pci_ops.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <soc/espi.h>
@@ -27,29 +26,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
#if ENV_RAMSTAGE
-static void soc_mirror_dmi_pcr_io_dec(void)
-{
- struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
- uint32_t io_dec_arr[] = {
- pci_read_config32(dev, ESPI_GEN1_DEC),
- pci_read_config32(dev, ESPI_GEN2_DEC),
- pci_read_config32(dev, ESPI_GEN3_DEC),
- pci_read_config32(dev, ESPI_GEN4_DEC),
- };
- /* Mirror these same settings in DMI PCR */
- soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
-}
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
@@ -70,7 +47,6 @@ void lpc_soc_init(struct device *dev)
pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
- soc_mirror_dmi_pcr_io_dec();
}
#endif
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 08edfeec16..18e611962b 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -33,9 +33,6 @@
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static void soc_config_pwrmbase(void)
{
/*
@@ -120,19 +117,8 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in ESPI PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
index fdcd83357e..489fe34223 100644
--- a/src/soc/intel/icelake/espi.c
+++ b/src/soc/intel/icelake/espi.c
@@ -9,7 +9,6 @@
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/irq.h>
@@ -27,29 +26,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
#if ENV_RAMSTAGE
-static void soc_mirror_dmi_pcr_io_dec(void)
-{
- struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
- uint32_t io_dec_arr[] = {
- pci_read_config32(dev, ESPI_GEN1_DEC),
- pci_read_config32(dev, ESPI_GEN2_DEC),
- pci_read_config32(dev, ESPI_GEN3_DEC),
- pci_read_config32(dev, ESPI_GEN4_DEC),
- };
- /* Mirror these same settings in DMI PCR */
- soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
-}
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
@@ -70,7 +47,6 @@ void lpc_soc_init(struct device *dev)
pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
- soc_mirror_dmi_pcr_io_dec();
}
/* Fill up ESPI IO resource structure inside SoC directory */
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index d98d5a8213..4dc5b08591 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -37,9 +37,6 @@
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static void soc_config_pwrmbase(void)
{
/*
@@ -121,19 +118,8 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in ESPI PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index 3911c81c3d..c3b50de8f0 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -9,7 +9,6 @@
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/irq.h>
@@ -27,29 +26,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
#if ENV_RAMSTAGE
-static void soc_mirror_dmi_pcr_io_dec(void)
-{
- struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
- uint32_t io_dec_arr[] = {
- pci_read_config32(dev, ESPI_GEN1_DEC),
- pci_read_config32(dev, ESPI_GEN2_DEC),
- pci_read_config32(dev, ESPI_GEN3_DEC),
- pci_read_config32(dev, ESPI_GEN4_DEC),
- };
- /* Mirror these same settings in DMI PCR */
- soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
-}
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
@@ -70,7 +47,6 @@ void lpc_soc_init(struct device *dev)
pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
- soc_mirror_dmi_pcr_io_dec();
}
#endif
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index a5bbb095b0..9fb2aa1b36 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -129,21 +129,8 @@ void pch_early_iorange_init(void)
}
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * As per PCH BWG 2.5.1.6.
- * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in LPC PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * As per PCH BWG 2.5.1.5.
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 6a22af8216..5abae765c9 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -7,7 +7,6 @@
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <soc/iomap.h>
#include <soc/pcr_ids.h>
@@ -25,15 +24,6 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
static const struct reg_script pch_misc_init_script[] = {
/* Enable BIOS updates outside of SMM */
REG_PCI_RMW8(0xdc, ~(1 << 5), 0),
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 5a63b40c21..96a4487f26 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -42,9 +42,6 @@
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_LPCIOD 0x2770
-#define PCR_DMI_LPCIOE 0x2774
-
static void soc_config_pwrmbase(void)
{
/*
@@ -126,19 +123,8 @@ void pch_early_iorange_init(void)
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in ESPI PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index 34847e8b78..8386cd9df1 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -15,7 +15,6 @@
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/irq.h>
@@ -33,29 +32,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
#if ENV_RAMSTAGE
-static void soc_mirror_dmi_pcr_io_dec(void)
-{
- struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
- uint32_t io_dec_arr[] = {
- pci_read_config32(dev, ESPI_GEN1_DEC),
- pci_read_config32(dev, ESPI_GEN2_DEC),
- pci_read_config32(dev, ESPI_GEN3_DEC),
- pci_read_config32(dev, ESPI_GEN4_DEC),
- };
- /* Mirror these same settings in DMI PCR */
- soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
-}
-
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
@@ -76,7 +53,6 @@ void lpc_soc_init(struct device *dev)
pch_pirq_init();
setup_i8259();
i8259_configure_irq_trigger(9, 1);
- soc_mirror_dmi_pcr_io_dec();
}
#endif
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index a8cecc5700..fac66f7881 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -39,8 +39,10 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
+ select SOC_INTEL_COMMON_BLOCK_DMI
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_LPC
+ select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index 268db92f9a..f0cb6db63d 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -3,7 +3,6 @@
#include <console/console.h>
#include <arch/ioapic.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <soc/iomap.h>
#include <soc/pcr_ids.h>
@@ -19,15 +18,6 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
void lpc_soc_init(struct device *dev)
{
printk(BIOS_SPEW, "pch: lpc_init\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 17:25:29 +0000