4 files changed, 29 insertions, 14 deletions

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 6a2349fb8d..2c7ec641b6 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -40,9 +40,19 @@ config CPU_SPECIFIC_OPTIONS
 #     The following options configure the debug serial port
 #####
 
+config ENABLE_BUILTIN_HSUART0
+	bool "Enable built-in HSUART0"
+	default n
+	select NO_UART_ON_SUPERIO
+	select DRIVERS_UART_8250MEM_32
+	help
+	  The Quark SoC has two HSUART. Choose this option to configure the pads
+	  and enable HSUART0, which can be used for the debug console.
+
 config ENABLE_BUILTIN_HSUART1
 	bool "Enable built-in HSUART1"
-	default y
+	default n
+	depends on ! ENABLE_BUILTIN_HSUART0
 	select NO_UART_ON_SUPERIO
 	select DRIVERS_UART_8250MEM_32
 	help
@@ -50,23 +60,24 @@ config ENABLE_BUILTIN_HSUART1
 	  and enable HSUART1, which can be used for the debug console.
 
 config TTYS0_BASE
-	hex "HSUART1 Base Address"
-	depends on ENABLE_BUILTIN_HSUART1
+	hex "HSUART Base Address"
 	default 0xA0019000
+	depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
 	help
-	  Memory mapped MMIO of HSUART1.
+	  Memory mapped MMIO of HSUART.
 
 config TTYS0_LCS
 	int
-	depends on ENABLE_BUILTIN_HSUART1
 	default 3
+	depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
 
-# Console: PCI UART bus 0 << 20, device 20 << 15, function 5 << 12
+# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
 #          Valid bit, PCI UART in use: 1 << 31
 config UART_PCI_ADDR
 	hex
-	depends on ENABLE_BUILTIN_HSUART1
-	default 0x800a5000
+	default 0x800a1000 if ENABLE_BUILTIN_HSUART0
+	default 0x800a5000 if ENABLE_BUILTIN_HSUART1
+	depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
 
 #####
 # Debug support
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 278a012d11..0c99eb9de4 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -33,11 +33,14 @@
 
 /* IO Fabric 1 */
 #define SIO1_DEV		0x14
+#define HSUART0_DEV		SIO1_DEV
 #define HSUART1_DEV		SIO1_DEV
+#define HSUART0_FUNC		1
 #define USB_DEV_PORT_FUNC	2
 #define EHCI_FUNC		3
 #define OHCI_FUNC		4
 #define HSUART1_FUNC		5
+#define HSUART0_BDF	PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART0_DEV, HSUART0_FUNC)
 #define HSUART1_BDF	PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC)
 
 /* IO Fabric 2 */
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index e7a8963b8c..b934032358 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -203,7 +203,6 @@ enum {
 	REG_USB_RXW(reg_, 0xffffffff, value_)
 
 void *get_i2c_address(void);
-void mainboard_gpio_init(void);
 void mainboard_gpio_pcie_reset(uint32_t pin_value);
 void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
 uint32_t mdr_read(void);
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 5be022a8d6..e27aa685be 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -67,6 +67,13 @@ static const struct reg_script hsuart_init[] = {
 
 void car_soc_pre_console_init(void)
 {
+	/* Initialize the controllers */
+	reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
+	reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
+
+	/* Enable the HSUART */
+	if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
+		reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
 	if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
 		reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
 }
@@ -74,11 +81,6 @@ void car_soc_pre_console_init(void)
 void car_soc_post_console_init(void)
 {
 	report_platform_info();
-
-	/* Initialize the controllers */
-	reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
-	reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
-	mainboard_gpio_init();
 };
 
 static struct chipset_power_state power_state CAR_GLOBAL;