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-rw-r--r--src/soc/intel/apollolake/gpio_apl.c6
-rw-r--r--src/soc/intel/common/block/gpio/gpio.c3
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio.h10
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio_defs.h14
4 files changed, 15 insertions, 18 deletions
diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c
index d7d3fe01f2..a774470fc5 100644
--- a/src/soc/intel/apollolake/gpio_apl.c
+++ b/src/soc/intel/apollolake/gpio_apl.c
@@ -22,9 +22,9 @@
#include <soc/pm.h>
static const struct reset_mapping rst_map[] = {
- { PAD_CFG0_RESET_PWROK, PAD_CFG0_RESET_PWROK },
- { PAD_CFG0_RESET_DEEP, PAD_CFG0_RESET_DEEP },
- { PAD_CFG0_RESET_PLTRST, PAD_CFG0_RESET_PLTRST },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
};
static const struct pad_community apl_gpio_communities[] = {
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 58bc6d9a81..6e9ae72c58 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -174,8 +174,7 @@ static uint32_t gpio_pad_reset_config_override(const struct pad_community *comm,
return config_value;/* Logical reset values equal chipset
values */
for (i = 0; i < comm->num_reset_vals; i++, rst_map++) {
- if ((config_value & PAD_CFG0_RESET_MASK) ==
- rst_map->logical) {
+ if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) {
config_value &= ~PAD_CFG0_RESET_MASK;
config_value |= rst_map->chipset;
return config_value;
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index c1542be6e7..879d30b469 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -45,12 +45,14 @@ struct pad_config {
};
/*
- * Structure provides the logical to actual value for PADRSTCFG in DW0
+ * Structure provides the logical to actual value for PADRSTCFG in DW0. Note
+ * that the values are expected to be within the field placement of the register
+ * itself. i.e. if the reset field is at 31:30 then the values within logical
+ * and chipset should occupy 31:30.
*/
struct reset_mapping {
- int logical;/* logical value defined in
- include/intelblocks/gpio_defs.h - PAD_CFG0_RESET_xxx */
- int chipset;/* translation of logical to SOC PADRSTCFG */
+ uint32_t logical;
+ uint32_t chipset;
};
/* This structure will be used to describe a community or each group within a
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index 5085af462d..244c680158 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -50,14 +50,10 @@
#define PAD_CFG0_RXRAW1_MASK (1 << 28)
#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29)
#define PAD_CFG0_RESET_MASK (3 << 30)
-#define PAD_CFG0_RESET_PWROK (0 << 30) /* Logical PADRSTCFG value */
-#define PAD_CFG0_RESET_DEEP (1 << 30) /* Logical PADRSTCFG value */
-#define PAD_CFG0_RESET_PLTRST (2 << 30) /* Logical PADRSTCFG value */
-#define PAD_CFG0_RESET_RSMRST (3 << 30) /* Logical PADRSTCFG value */
-/* The PAD_CFG0_RESET_xxx are logical values and the actual chipset values
- corresponding to these will be replaced by code in
- soc/intel/common/block/gpio
- */
+#define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30)
+#define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
+#define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
+#define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
/* Use the fourth bit in IntSel field to indicate gpio
* ownership. This field is RO and hence not used during
@@ -118,7 +114,7 @@
#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */
#define PAD_FUNC(value) PAD_CFG0_MODE_##value
-#define PAD_RESET(value) PAD_CFG0_RESET_##value
+#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value
#define PAD_PULL(value) PAD_CFG1_PULL_##value
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY)