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-rw-r--r--src/soc/intel/apollolake/meminit.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 9e6622cc1b..889bbde66d 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -69,7 +69,7 @@ size_t iohole_in_mib(void)
return 2 * (GiB / MiB);
}
-static void set_lpddr4_defaults(FSP_M_CONFIG *cfg, int speed)
+static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
{
uint8_t odt_config;
@@ -126,10 +126,6 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg, int speed)
up to 1.1V. */
odt_config = ODT_A_B_HIGH_HIGH;
- /* Need to set correct Write-Recovery configuration based on speed. */
- if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && speed >= LP4_SPEED_2133)
- odt_config |= nWR_24;
-
cfg->Ch0_OdtConfig = odt_config;
cfg->Ch1_OdtConfig = odt_config;
cfg->Ch2_OdtConfig = odt_config;
@@ -213,7 +209,7 @@ void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed);
cfg->Profile = fsp_memory_profile(speed);
- set_lpddr4_defaults(cfg, speed);
+ set_lpddr4_defaults(cfg);
}
static void enable_logical_chan0(FSP_M_CONFIG *cfg,