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-rw-r--r--src/soc/intel/tigerlake/chip.h3
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c1
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6a48ad03be..5c124de492 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -242,6 +242,9 @@ struct soc_intel_tigerlake_config {
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+ /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
+ uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
+
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 6de098aa3e..ed34897274 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -187,6 +187,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i];
params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+ params->PciePtm[i] = config->PciePtm[i];
}
/* Enable ClkReqDetect for enabled port */