diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 7 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0c4232c277..924764a6c8 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -295,7 +295,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; - params->SkipMpInit = config->FspSkipMpInit; + params->SkipMpInit = !config->use_fsp_mp_init; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 8fdb9646b3..d943f9c781 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -206,7 +206,12 @@ struct soc_intel_cannonlake_config { CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ } chipset_lockdown; - uint8_t FspSkipMpInit; + /* + * Option for mainboard to skip coreboot MP initialization + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ + uint8_t use_fsp_mp_init; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ |