diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/quark/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/ramstage.h | 25 | ||||
| -rw-r--r-- | src/soc/intel/quark/northcluster.c | 78 |
4 files changed, 105 insertions, 2 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index e5594bee95..f107fdf6c6 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -24,6 +24,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c ramstage-y += chip.c ramstage-y += memmap.c +ramstage-y += northcluster.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 61c0803c5f..3e11225b45 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -14,10 +14,9 @@ * GNU General Public License for more details. */ -#include "chip.h" #include <console/console.h> #include <device/device.h> -#include <fsp/ramstage.h> +#include <soc/ramstage.h> static void chip_init(void *chip_info) { diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h new file mode 100644 index 0000000000..19b27a86d4 --- /dev/null +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <chip.h> +#include <device/device.h> +#include <fsp/ramstage.h> +#include <soc/QuarkNcSocId.h> + +#endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c new file mode 100644 index 0000000000..90ea256708 --- /dev/null +++ b/src/soc/intel/quark/northcluster.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/ramstage.h> + +#define RES_IN_KIB(r) ((r) >> 10) + +static void nc_read_resources(device_t dev) +{ + unsigned long base_k; + int index = 0; + unsigned long size_k; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* 0 -> 0xa0000 */ + base_k = 0; + size_k = 0xa0000 - base_k; + ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); + + /* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xdffff: RAM + * 0xe0000 - 0xfffff: ROM shadow + */ + base_k += size_k; + size_k = 0xc0000 - base_k; + mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); + + base_k += size_k; + size_k = 0x100000 - base_k; + reserved_ram_resource(dev, index++, RES_IN_KIB(base_k), + RES_IN_KIB(size_k)); + + /* 0x100000 -> cbmem_top - cacheable and usable */ + base_k += size_k; + size_k = (unsigned long)cbmem_top() - base_k; + ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); + + /* cbmem_top -> 4GiB is mmio. */ + base_k += size_k; + size_k = 0x100000000ull - base_k; + mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); +} + +static struct device_operations nc_ops = { + .read_resources = &nc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, +}; + +static const struct pci_driver systemagent_driver __pci_driver = { + .ops = &nc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = QUARK_MC_DEVICE_ID +}; |