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-rw-r--r--src/soc/intel/baytrail/include/soc/romstage.h2
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c2
-rw-r--r--src/soc/intel/braswell/pmutil.c12
-rw-r--r--src/soc/intel/braswell/ramstage.c2
-rw-r--r--src/soc/intel/cannonlake/bootblock/report_platform.c2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pmclib.h6
-rw-r--r--src/soc/intel/denverton_ns/pmutil.c10
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c2
-rw-r--r--src/soc/intel/fsp_broadwell_de/pmutil.c6
-rw-r--r--src/soc/intel/skylake/bootblock/report_platform.c2
-rw-r--r--src/soc/intel/skylake/me.c16
11 files changed, 31 insertions, 31 deletions
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index a3f1fc7dac..ba12c8f75a 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -31,7 +31,7 @@ struct romstage_params {
void mainboard_romstage_entry(struct romstage_params *params);
void romstage_common(struct romstage_params *params);
-void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
+void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
uint32_t tsc_high);
void asmlinkage romstage_after_car(void);
void raminit(struct mrc_params *mp, int prev_sleep_state);
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index e38957eaf0..c971b353df 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -98,7 +98,7 @@ static void spi_init(void)
}
/* Entry from cache-as-ram.inc. */
-void * asmlinkage romstage_main(unsigned long bist,
+void *asmlinkage romstage_main(unsigned long bist,
uint32_t tsc_low, uint32_t tsc_hi)
{
struct romstage_params rp = {
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 5f078dfbcf..00284d1604 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -53,7 +53,7 @@ uint16_t get_pmbase(void)
}
static void print_num_status_bits(int num_bits, uint32_t status,
- const char * const bit_names[])
+ const char *const bit_names[])
{
int i;
@@ -72,7 +72,7 @@ static void print_num_status_bits(int num_bits, uint32_t status,
static uint32_t print_smi_status(uint32_t smi_sts)
{
- static const char * const smi_sts_bits[] = {
+ static const char *const smi_sts_bits[] = {
[2] = "BIOS",
[4] = "SLP_SMI",
[5] = "APM",
@@ -157,7 +157,7 @@ static uint16_t reset_pm1_status(void)
static uint16_t print_pm1_status(uint16_t pm1_sts)
{
- static const char * const pm1_sts_bits[] = {
+ static const char *const pm1_sts_bits[] = {
[0] = "TMROF",
[5] = "GBL",
[8] = "PWRBTN",
@@ -190,7 +190,7 @@ void enable_pm1(uint16_t events)
static uint32_t print_tco_status(uint32_t tco_sts)
{
- static const char * const tco_sts_bits[] = {
+ static const char *const tco_sts_bits[] = {
[3] = "TIMEOUT",
[17] = "SECOND_TO",
};
@@ -252,7 +252,7 @@ static uint32_t reset_gpe_status(void)
static uint32_t print_gpe_sts(uint32_t gpe_sts)
{
- static const char * const gpe_sts_bits[] = {
+ static const char *const gpe_sts_bits[] = {
[1] = "HOTPLUG",
[2] = "SWGPE",
[3] = "PCIE_WAKE0",
@@ -308,7 +308,7 @@ static uint32_t reset_alt_status(void)
static uint32_t print_alt_sts(uint32_t alt_gpio_smi)
{
uint32_t alt_gpio_sts;
- static const char * const alt_gpio_smi_sts_bits[] = {
+ static const char *const alt_gpio_smi_sts_bits[] = {
[0] = "SUS_GPIO_0",
[1] = "SUS_GPIO_1",
[2] = "SUS_GPIO_2",
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 3ab1af3b54..4559739987 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -72,7 +72,7 @@ static inline void fill_in_msr(msr_t *msr, int idx)
}
}
-static const char * const stepping_str[] = {
+static const char *const stepping_str[] = {
"A0", "A1", "B0", "B1", "B2", "B3", "C0"
};
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index a2cd864cf3..9d967cee68 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -86,7 +86,7 @@ static void report_cpu_info(void)
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
- static const char * const mode[] = {"NOT ", ""};
+ static const char *const mode[] = {"NOT ", ""};
const char *cpu_type = "Unknown";
u32 p[13];
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index ddf384b56b..9b21010064 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -91,7 +91,7 @@ uint32_t pmc_clear_tco_status(void);
* names for the TCO status bits. Size of the array is
* returned as an output parameter.
*/
-const char * const *soc_tco_sts_array(size_t *a);
+const char *const *soc_tco_sts_array(size_t *a);
/*
* Resets the tco status registers. This function clears the tco_sts register
@@ -186,14 +186,14 @@ uintptr_t soc_read_pmc_base(void);
* names for the SMI status register bits. Size of the array is
* returned as an output parameter.
*/
-const char * const *soc_smi_sts_array(size_t *a);
+const char *const *soc_smi_sts_array(size_t *a);
/*
* This function returns array of string which represents
* names for the STD GPE status register bits.
* Size of the array is returned as an output parameter.
*/
-const char * const *soc_std_gpe_sts_array(size_t *a);
+const char *const *soc_std_gpe_sts_array(size_t *a);
/*
* This function gets the gpe0 dwX values from devicetree
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index 542997c6c6..78903bbc35 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -24,7 +24,7 @@
#include <soc/pm.h>
static void print_num_status_bits(int num_bits, uint32_t status,
- const char * const bit_names[])
+ const char *const bit_names[])
{
int i;
@@ -43,7 +43,7 @@ static void print_num_status_bits(int num_bits, uint32_t status,
static uint32_t print_smi_status(uint32_t smi_sts)
{
- static const char * const smi_sts_bits[] = {
+ static const char *const smi_sts_bits[] = {
[2] = "BIOS",
[4] = "SLP_SMI",
[5] = "APM",
@@ -129,7 +129,7 @@ static uint16_t reset_pm1_status(void)
static uint16_t print_pm1_status(uint16_t pm1_sts)
{
- static const char * const pm1_sts_bits[] = {
+ static const char *const pm1_sts_bits[] = {
[0] = "TMROF", [4] = "BM", [5] = "GBL",
[8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
[15] = "WAK",
@@ -155,7 +155,7 @@ void enable_pm1(uint16_t events)
static uint32_t print_tco_status(uint32_t tco_sts)
{
- static const char * const tco_sts_bits[] = {
+ static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
[2] = "TCO_INIT", [3] = "TIMEOUT",
[7] = "NEWCENTURY ", [8] = "BIOSWR ",
@@ -214,7 +214,7 @@ static uint32_t reset_gpe_status(void)
static uint32_t print_gpe_sts(uint32_t gpe_sts)
{
- static const char * const gpe_sts_bits[] = {
+ static const char *const gpe_sts_bits[] = {
[0] = "GPIO_0", [1] = "GPIO_1",
[2] = "GPIO_2", [3] = "GPIO_3",
[4] = "GPIO_4", [5] = "GPIO_5",
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c7c984c5e7..a7268aa20b 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -44,7 +44,7 @@ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
UPD_DATA_REGION *UpdDataRgnPtr;
VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase);
UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
- memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+ memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
}
/* default to just enabling HDMI audio */
diff --git a/src/soc/intel/fsp_broadwell_de/pmutil.c b/src/soc/intel/fsp_broadwell_de/pmutil.c
index bd19104f4d..ccab1cef33 100644
--- a/src/soc/intel/fsp_broadwell_de/pmutil.c
+++ b/src/soc/intel/fsp_broadwell_de/pmutil.c
@@ -29,7 +29,7 @@
#include <soc/pci_devs.h>
/* Print status bits with descriptive names */
-static void print_status_bits(u32 status, const char * const bit_names[])
+static void print_status_bits(u32 status, const char *const bit_names[])
{
int i;
@@ -73,7 +73,7 @@ static u16 reset_pm1_status(void)
/* Print PM1 status bits */
static u16 print_pm1_status(u16 pm1_sts)
{
- static const char * const pm1_sts_bits[] = {
+ static const char *const pm1_sts_bits[] = {
[0] = "TMROF",
[4] = "BM",
[5] = "GBL",
@@ -117,7 +117,7 @@ static u32 reset_smi_status(void)
/* Print SMI status bits */
static u32 print_smi_status(u32 smi_sts)
{
- static const char * const smi_sts_bits[] = {
+ static const char *const smi_sts_bits[] = {
[2] = "BIOS",
[3] = "LEGACY_USB",
[4] = "SLP_SMI",
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index 8fd6599fb1..7d5bc3fb2a 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -121,7 +121,7 @@ static void report_cpu_info(void)
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
- static const char * const mode[] = {"NOT ", ""};
+ static const char *const mode[] = {"NOT ", ""};
const char *cpu_type = "Unknown";
index = 0x80000000;
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index a23172e60c..632749d071 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -34,7 +34,7 @@ static inline u32 me_read_config32(int offset)
}
/* HFSTS1[3:0] Current Working State Values */
-static const char * const me_cws_values[] = {
+static const char *const me_cws_values[] = {
[ME_HFS_CWS_RESET] = "Reset",
[ME_HFS_CWS_INIT] = "Initializing",
[ME_HFS_CWS_REC] = "Recovery",
@@ -54,7 +54,7 @@ static const char * const me_cws_values[] = {
};
/* HFSTS1[8:6] Current Operation State Values */
-static const char * const me_opstate_values[] = {
+static const char *const me_opstate_values[] = {
[ME_HFS_STATE_PREBOOT] = "Preboot",
[ME_HFS_STATE_M0_UMA] = "M0 with UMA",
[ME_HFS_STATE_M3] = "M3 without UMA",
@@ -64,7 +64,7 @@ static const char * const me_opstate_values[] = {
};
/* HFSTS1[19:16] Current Operation Mode Values */
-static const char * const me_opmode_values[] = {
+static const char *const me_opmode_values[] = {
[ME_HFS_MODE_NORMAL] = "Normal",
[ME_HFS_MODE_DEBUG] = "Debug",
[ME_HFS_MODE_DIS] = "Soft Temporary Disable",
@@ -73,7 +73,7 @@ static const char * const me_opmode_values[] = {
};
/* HFSTS1[15:12] Error Code Values */
-static const char * const me_error_values[] = {
+static const char *const me_error_values[] = {
[ME_HFS_ERROR_NONE] = "No Error",
[ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
[ME_HFS_ERROR_IMAGE] = "Image Failure",
@@ -81,7 +81,7 @@ static const char * const me_error_values[] = {
};
/* HFSTS2[31:28] ME Progress Code */
-static const char * const me_progress_values[] = {
+static const char *const me_progress_values[] = {
[ME_HFS2_PHASE_ROM] = "ROM Phase",
[1] = "Unknown (1)",
[ME_HFS2_PHASE_UKERNEL] = "uKernel Phase",
@@ -94,7 +94,7 @@ static const char * const me_progress_values[] = {
};
/* HFSTS2[27:24] Power Management Event */
-static const char * const me_pmevent_values[] = {
+static const char *const me_pmevent_values[] = {
[ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] =
"Clean Moff->Mx wake",
[ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] =
@@ -131,13 +131,13 @@ static const char * const me_pmevent_values[] = {
};
/* Progress Code 0 states */
-static const char * const me_progress_rom_values[] = {
+static const char *const me_progress_rom_values[] = {
[ME_HFS2_STATE_ROM_BEGIN] = "BEGIN",
[ME_HFS2_STATE_ROM_DISABLE] = "DISABLE"
};
/* Progress Code 1 states */
-static const char * const me_progress_bup_values[] = {
+static const char *const me_progress_bup_values[] = {
[ME_HFS2_STATE_BUP_INIT] =
"Initialization starts",
[ME_HFS2_STATE_BUP_DIS_HOST_WAKE] =
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-08 20:15:19 +0000