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-rw-r--r--src/soc/intel/tigerlake/chip.h6
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c6
2 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 3f980d1552..4f57b0e07a 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -218,6 +218,10 @@ struct soc_intel_tigerlake_config {
FORCE_ENABLE,
} CnviBtAudioOffload;
+ /* Tcss */
+ uint8_t TcssXhciEn;
+ uint8_t TcssXdciEn;
+
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 9c105cadc2..fc3155f8ad 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -105,6 +105,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Image clock: disable all clocks for bypassing FSP pin mux */
memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
+ /* Tcss */
+ m_cfg->TcssXhciEn = config->TcssXhciEn;
+ m_cfg->TcssXdciEn = config->TcssXdciEn;
+
/* Enable Hyper Threading */
m_cfg->HyperThreading = 1;
/* Disable Lock PCU Thermal Management registers */