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-rw-r--r--src/soc/intel/tigerlake/chip.h23
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c24
2 files changed, 41 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index fee7105245..59dab58bb8 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -133,6 +133,23 @@ struct soc_intel_tigerlake_config {
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
+ /*
+ * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
+ * Default 0. Setting this to 1 disables the SATA Power Optimizer.
+ */
+ uint8_t SataPwrOptimizeDisable;
+
+ /*
+ * SATA Port Enable Dito Config.
+ * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
+ */
+ uint8_t SataPortsEnableDitoConfig[8];
+
+ /* SataPortsDmVal is the DITO multiplier. Default is 15. */
+ uint8_t SataPortsDmVal[8];
+ /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
+ uint16_t SataPortsDitoVal[8];
+
/* Audio related */
uint8_t PchHdaDspEnable;
uint8_t PchHdaAudioLinkHdaEnable;
@@ -337,12 +354,6 @@ struct soc_intel_tigerlake_config {
*/
uint8_t DmiPwrOptimizeDisable;
- /*
- * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
- * Default 0. Setting this to 1 disables the SATA Power Optimizer.
- */
- uint8_t SataPwrOptimizeDisable;
-
/* structure containing various settings for PCH FIVRs */
struct {
bool configure_ext_fivr;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 3187a33eaf..798c16a425 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -24,6 +24,10 @@
#define THC_0 1
#define THC_1 2
+/* SATA DEVSLP idle timeout default values */
+#define DEF_DMVAL 15
+#define DEF_DITOVAL 625
+
/*
* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
* because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@@ -212,6 +216,26 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+ /*
+ * Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
+ * SataPortsDmVal is the DITO multiplier. Default is 15.
+ * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
+ * The default values can be changed from devicetree.
+ */
+ for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
+ if (config->SataPortsEnableDitoConfig[i]) {
+ if (config->SataPortsDmVal[i])
+ params->SataPortsDmVal[i] = config->SataPortsDmVal[i];
+ else
+ params->SataPortsDmVal[i] = DEF_DMVAL;
+
+ if (config->SataPortsDitoVal[i])
+ params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
+ else
+ params->SataPortsDitoVal[i] = DEF_DITOVAL;
+ }
+ }
+
/* Enable TCPU for processor thermal control */
params->Device4Enable = config->Device4Enable;