diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 23 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index f3f700f146..a8be407d23 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -186,6 +186,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Hybrid storage auto detection */ params->HybridStorageMode = config->HybridStorageMode; + /* USB4/TBT */ + for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { + dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); + if (dev) + params->ITbtPcieRootPortEn[i] = dev->enabled; + else + params->ITbtPcieRootPortEn[i] = 0; + } + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index e275e59fcc..95f637e4ec 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -120,6 +120,29 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + /* USB4/TBT */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + if (dev) + m_cfg->TcssItbtPcie0En = dev->enabled; + else + m_cfg->TcssItbtPcie0En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + if (dev) + m_cfg->TcssItbtPcie1En = dev->enabled; + else + m_cfg->TcssItbtPcie1En = 0; + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + if (dev) + m_cfg->TcssItbtPcie2En = dev->enabled; + else + m_cfg->TcssItbtPcie2En = 0; + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + if (dev) + m_cfg->TcssItbtPcie3En = dev->enabled; + else + m_cfg->TcssItbtPcie3En = 0; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ |