2 files changed, 31 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h
index 71f9c6255d..819b9403a3 100644
--- a/src/soc/intel/common/block/include/intelblocks/p2sb.h
+++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h
@@ -29,6 +29,18 @@ void p2sb_disable_sideband_access(void);
 void p2sb_enable_bar(void);
 void p2sb_configure_hpet(void);
 
+union p2sb_bdf {
+	struct {
+		uint16_t fn  : 3;
+		uint16_t dev : 5;
+		uint16_t bus : 8;
+	};
+	uint16_t raw;
+};
+
+union p2sb_bdf p2sb_get_hpet_bdf(void);
+void p2sb_set_hpet_bdf(union p2sb_bdf bdf);
+
 /* SOC overrides */
 /*
  * Each SoC should implement EP Mask register to disable SB access
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 9673a2cf71..fd54a08dda 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -54,6 +54,25 @@ void p2sb_configure_hpet(void)
 	pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
 }
 
+union p2sb_bdf p2sb_get_hpet_bdf(void)
+{
+	const bool was_hidden = p2sb_is_hidden();
+	if (was_hidden)
+		p2sb_unhide();
+
+	union p2sb_bdf bdf = { .raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF) };
+
+	if (was_hidden)
+		p2sb_hide();
+
+	return bdf;
+}
+
+void p2sb_set_hpet_bdf(union p2sb_bdf bdf)
+{
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, bdf.raw);
+}
+
 static void p2sb_set_hide_bit(int hide)
 {
 	const uint16_t reg = PCH_P2SB_E0 + 1;