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-rw-r--r--src/soc/intel/elkhartlake/chip.h3
-rw-r--r--src/soc/intel/elkhartlake/cpu.c8
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index d63844ffe7..94a2cdff78 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -454,6 +454,9 @@ struct soc_intel_elkhartlake_config {
* 3600, 3733, 4000, 4200, 4267 and 0 for Auto.
*/
uint16_t max_dram_speed_mts;
+
+ /* Disable L1 prefetcher */
+ bool L1_prefetcher_disable;
};
typedef struct soc_intel_elkhartlake_config config_t;
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index f4baa65fd9..8ba28c0159 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -67,6 +67,14 @@ static void configure_misc(void)
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
msr.lo |= (1 << 23); /* Lock it */
wrmsr(MSR_POWER_CTL, msr);
+
+ /* In some cases it is beneficial for the performance to disable the
+ L1 prefetcher as on Elkhart Lake it is set up a bit too aggressive. */
+ if (conf->L1_prefetcher_disable) {
+ msr = rdmsr(MSR_PREFETCH_CTL);
+ msr.lo |= PREFETCH_L1_DISABLE;
+ wrmsr(MSR_PREFETCH_CTL, msr);
+ }
}
/* All CPUs including BSP will run the following function. */