4 files changed, 698 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
new file mode 100644
index 0000000000..4093599aca
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_PMCLIB_H
+#define SOC_INTEL_COMMON_BLOCK_PMCLIB_H
+
+#include <stdint.h>
+
+/* Forward declare the power state struct here */
+struct chipset_power_state;
+
+/*
+ * This is implemented as weak function in common pmc lib.
+ * Clears all power management related registers as the boot
+ * flow is past the point of needing to maintain the values.
+ */
+void soc_clear_pm_registers(uintptr_t pmc_bar);
+
+/*
+ * This is implemented as weak function in common pmc lib and deals with any
+ * soc specific quarks. Returns SMI status bits.
+ */
+uint32_t soc_get_smi_status(uint32_t generic_sts);
+
+/*
+ * This function is specific to soc and is defined as weak in common
+ * pmclib file. SOC code can implement it for any special condition
+ * specific to the soc e.g. in SKL in handles deep S3 scenerio.
+ * Return ACPI_SX values to indicate the previous sleep state.
+ */
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+					int prev_sleep_state);
+/*
+ * Function to print, clear, and return SMI status bits in SMI_STS
+ * register. This function internally calls pmc_reset_smi_status with
+ * extra functionality of printing the set smi_sts bits.
+ */
+uint32_t pmc_clear_smi_status(void);
+
+/*
+ * Function to return the 32 bit value of SMI control and enable register
+ * used to check which smi's are enabled.
+ */
+uint32_t pmc_get_smi_en(void);
+
+/* Enable SMI event in SMI control and enable register */
+void pmc_enable_smi(uint32_t mask);
+
+/* Disable SMI event */
+void pmc_disable_smi(uint32_t mask);
+
+/* Enable events in PM1 control register */
+void pmc_enable_pm1_control(uint32_t mask);
+
+/* Disable events in PM1 control register*/
+void pmc_disable_pm1_control(uint32_t mask);
+
+/* Set the PM1 register to events in PM1_STS_EN register */
+void pmc_enable_pm1(uint16_t events);
+
+/* Print, clear, and return PM1 status */
+uint16_t pmc_clear_pm1_status(void);
+
+/* TCO */
+
+/* Print, clear, and return TCO status */
+uint32_t pmc_clear_tco_status(void);
+
+/*
+ * This function returns array of string which represents
+ * names for the TCO status bits. Size of the array is
+ * returned as an output parameter.
+ */
+const char * const *soc_tco_sts_array(size_t *a);
+
+/*
+ * Resets the tco status registers. This function clears the tco_sts register
+ * and returns the sts and enable bits set.
+ */
+uint32_t soc_reset_tco_status(void);
+
+
+/* GPE */
+
+/*
+ * We have gpe0a_en/sts, gpe0b_en/sts, gpe0c_en/sts and gpe0d_en/sts
+ * registers. gpe0a_en is symmetrical to the general purpose event
+ * 0a status register and have all the enable bits for
+ * gpe's. Other gpe registers gpe0b_en, gpe0c_en and
+ * gpe0d_en are symmetrical to general purpose event status
+ * registers and reads/writes to those register will result in
+ * the transaction being forwarded to the corresponding GPIO
+ * community based on the GPIO_GPE_CFG.gpe0_dw1, GPIO_GPE_CFG.gpe0_dw2
+ * and GPIO_GPE_CFG.gpe0_dw3 register configuration.
+ *
+ * STS registers are symmetrical to event enable registers.
+ * For gpe0a_sts register if the corresponding _EN bit is set in gpe0a_en,
+ * then when the STS bit get set, the PMC will generate a Wake Event.
+ * Once back in an S0 state (or if already in an S0 state when the event
+ * occurs), the PMC will also generate an SCI if the SCI_EN bit is set,
+ * or an SMI# if the SCI_EN bit is not set. Other gpe registers gpe0b_sts,
+ * gpe0c_sts and gpe0d_sts are symmetrical to general purpose event enable
+ * registers and reads/writes to those register will result in
+ * the transaction being forwarded to the corresponding GPIO
+ * community based on the GPIO_GPE_CFG.gpe0_dw1, GPIO_GPE_CFG.gpe0_dw2 and
+ * GPIO_GPE_CFG.gpe0_dw3 register configuration.
+ */
+/* Enable a standard GPE in gpe0_en register */
+void pmc_enable_gpe(uint32_t mask);
+/* Disable a standard GPE in gpe0a_en register */
+void pmc_disable_gpe(uint32_t mask);
+/* Disable all GPE's in gpe0a_en register */
+void pmc_disable_all_gpe(void);
+/* Clear all GPE status and return "standard" GPE event status */
+uint32_t pmc_clear_gpe_status(void);
+/* Clear status bits in Power and Reset Status (PRSTS) register */
+void pmc_clear_status(void);
+/* Clear the gpio gpe0 status bits in ACPI registers */
+void pmc_clear_gpi_gpe_sts(void);
+
+/*
+ * Enable or disable global reset. If global reset is enabled, hard reset and
+ * soft reset will trigger global reset, where both host and TXE are reset.
+ * This is cleared on cold boot, hard reset, soft reset and Sx.
+ */
+void pmc_global_reset_enable(bool enable);
+/*
+ * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
+ * This lock is reset on cold boot, hard reset, soft reset and Sx.
+ */
+void pmc_global_reset_lock(void);
+
+/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */
+void pmc_fixup_power_state(void);
+
+/*
+ * Reads and prints ACPI specific PM registers which are common across
+ * chipsets. Returns the previous sleep state which is one of ACPI_SX values.
+ */
+int pmc_fill_power_state(struct chipset_power_state *ps);
+
+/*
+ * Sets the gpe routing table by properly programming the GPE_CFG
+ * and the MISCCFG registers. This function calls soc specific
+ * soc_get_gpe_configs which reads the devicetree info
+ * and populates the dw variables and also returns the bit offset
+ * in GPIO_CFG register which is assigned to ACPI register.
+ */
+void pmc_gpe_init(void);
+
+/* Power Management Utility Functions. */
+
+/* Returns PMC base address */
+uintptr_t soc_read_pmc_base(void);
+
+/*
+ * This function returns array of string which represents
+ * names for the SMI status register bits. Size of the array is
+ * returned as an output parameter.
+ */
+const char * const *soc_smi_sts_array(size_t *a);
+
+/*
+ * This function returns array of string which represents
+ * names for the General purpose Event status register bits.
+ * Size of the array is returned as an output parameter.
+ */
+const char * const *soc_gpe_sts_array(size_t *a);
+
+/*
+ * This function gets the gpe0 dwX values from devicetree
+ * for pmc_gpe_init which will use those to set the GPE_CFG
+ * register.
+ */
+void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);
+
+/*
+ * Reads soc specific power management crtitical registers, fills
+ * chipset_power_state structure variable and prints.
+ */
+void soc_fill_power_state(struct chipset_power_state *ps);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
new file mode 100644
index 0000000000..4e10f93537
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -0,0 +1,6 @@
+config SOC_INTEL_COMMON_BLOCK_PMC
+	depends on SOC_INTEL_COMMON_BLOCK_GPIO
+	bool
+	help
+	  Intel Processor common code for Power Management controller(PMC)
+	  subsystem
diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc
new file mode 100644
index 0000000000..40fcba10f7
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
new file mode 100644
index 0000000000..e741332f88
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -0,0 +1,492 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <halt.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/gpio.h>
+#include <soc/pm.h>
+#include <timer.h>
+#include <vboot/vboot_common.h>
+
+static void print_num_status_bits(int num_bits, uint32_t status,
+				  const char *const bit_names[])
+{
+	int i;
+
+	if (!status)
+		return;
+
+	for (i = num_bits - 1; i >= 0; i--) {
+		if (status & (1 << i)) {
+			if (bit_names[i])
+				printk(BIOS_DEBUG, "%s ", bit_names[i]);
+			else
+				printk(BIOS_DEBUG, "BIT%d ", i);
+		}
+	}
+}
+
+__attribute__ ((weak)) uint32_t soc_get_smi_status(uint32_t generic_sts)
+{
+	return generic_sts;
+}
+
+static uint32_t pmc_reset_smi_status(void)
+{
+	uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
+	outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
+
+	return soc_get_smi_status(smi_sts);
+}
+
+static uint32_t print_smi_status(uint32_t smi_sts)
+{
+	size_t array_size;
+	const char *const *smi_arr;
+
+	if (!smi_sts)
+		return 0;
+
+	printk(BIOS_DEBUG, "SMI_STS: ");
+
+	smi_arr = soc_smi_sts_array(&array_size);
+
+	print_num_status_bits(array_size, smi_sts, smi_arr);
+	printk(BIOS_DEBUG, "\n");
+
+	return smi_sts;
+}
+
+uint32_t pmc_clear_smi_status(void)
+{
+	uint32_t sts = pmc_reset_smi_status();
+
+	return print_smi_status(sts);
+}
+
+uint32_t pmc_get_smi_en(void)
+{
+	return inl(ACPI_BASE_ADDRESS + SMI_EN);
+}
+
+void pmc_enable_smi(uint32_t mask)
+{
+	uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
+	smi_en |= mask;
+	outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
+}
+
+void pmc_disable_smi(uint32_t mask)
+{
+	uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
+	smi_en &= ~mask;
+	outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
+}
+
+/* PM1 */
+void pmc_enable_pm1(uint16_t events)
+{
+	outw(events, ACPI_BASE_ADDRESS + PM1_EN);
+}
+
+void pmc_enable_pm1_control(uint32_t mask)
+{
+	uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	pm1_cnt |= mask;
+	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+}
+
+void pmc_disable_pm1_control(uint32_t mask)
+{
+	uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	pm1_cnt &= ~mask;
+	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
+}
+
+static uint16_t reset_pm1_status(void)
+{
+	uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+	outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
+	return pm1_sts;
+}
+
+static uint16_t print_pm1_status(uint16_t pm1_sts)
+{
+	static const char *const pm1_sts_bits[] = {
+		[0] = "TMROF",
+		[5] = "GBL",
+		[8] = "PWRBTN",
+		[10] = "RTC",
+		[11] = "PRBTNOR",
+		[13] = "USB",
+		[14] = "PCIEXPWAK",
+		[15] = "WAK",
+	};
+
+	if (!pm1_sts)
+		return 0;
+
+	printk(BIOS_SPEW, "PM1_STS: ");
+	print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
+	printk(BIOS_SPEW, "\n");
+
+	return pm1_sts;
+}
+
+uint16_t pmc_clear_pm1_status(void)
+{
+	return print_pm1_status(reset_pm1_status());
+}
+
+/* TCO */
+
+static uint32_t print_tco_status(uint32_t tco_sts)
+{
+	size_t array_size;
+	const char *const *tco_arr;
+
+	if (!tco_sts)
+		return 0;
+
+	printk(BIOS_DEBUG, "TCO_STS: ");
+
+	tco_arr = soc_tco_sts_array(&array_size);
+
+	print_num_status_bits(array_size, tco_sts, tco_arr);
+	printk(BIOS_DEBUG, "\n");
+
+	return tco_sts;
+}
+
+uint32_t pmc_clear_tco_status(void)
+{
+	return print_tco_status(soc_reset_tco_status());
+}
+
+/* GPE */
+void pmc_enable_gpe(uint32_t mask)
+{
+	uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+	gpe0a_en |= mask;
+	outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+}
+
+void pmc_disable_gpe(uint32_t mask)
+{
+	uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+	gpe0a_en &= ~mask;
+	outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+}
+
+void pmc_disable_all_gpe(void)
+{
+	pmc_disable_gpe(~0);
+}
+
+/* Clear the gpio gpe0 status bits in ACPI registers */
+void pmc_clear_gpi_gpe_sts(void)
+{
+	int i;
+
+	for (i = 0; i < GPE0_REG_MAX; i++) {
+		/* This is reserved GPE block and specific to chipset */
+		if (i == GPE_STD)
+			continue;
+		uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
+		outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i));
+	}
+}
+
+static uint32_t reset_gpe_status(void)
+{
+	uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
+	outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
+	return gpe_sts;
+}
+
+static uint32_t print_gpe_sts(uint32_t gpe_sts)
+{
+	size_t array_size;
+	const char *const *sts_arr;
+
+	if (!gpe_sts)
+		return gpe_sts;
+
+	printk(BIOS_DEBUG, "GPE0a_STS: ");
+
+	sts_arr = soc_gpe_sts_array(&array_size);
+	print_num_status_bits(array_size, gpe_sts, sts_arr);
+	printk(BIOS_DEBUG, "\n");
+
+	return gpe_sts;
+}
+
+uint32_t pmc_clear_gpe_status(void)
+{
+	return print_gpe_sts(reset_gpe_status());
+}
+
+__attribute__ ((weak))
+void soc_clear_pm_registers(uintptr_t pmc_bar)
+{
+}
+
+void pmc_clear_status(void)
+{
+	uint32_t prsts;
+	uintptr_t pmc_bar;
+
+	/* Read PMC base address from soc */
+	pmc_bar = soc_read_pmc_base();
+
+	prsts = read32((void *)(pmc_bar + PRSTS));
+	write32((void *)(pmc_bar + PRSTS), prsts);
+
+	soc_clear_pm_registers(pmc_bar);
+}
+
+__attribute__ ((weak))
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+			      int prev_sleep_state)
+{
+	return prev_sleep_state;
+}
+
+/*
+ * Returns prev_sleep_state and also prints all power management registers.
+ * Calls soc_prev_sleep_state which may be impelmented by SOC.
+ */
+static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
+{
+	/* Default to S0. */
+	int prev_sleep_state = ACPI_S0;
+
+	if (ps->pm1_sts & WAK_STS) {
+		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
+		case ACPI_S3:
+			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+				prev_sleep_state = ACPI_S3;
+			break;
+		case ACPI_S5:
+			prev_sleep_state = ACPI_S5;
+			break;
+		}
+
+		/* Clear SLP_TYP. */
+		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+	}
+	return soc_prev_sleep_state(ps, prev_sleep_state);
+}
+
+/*
+ * This function re-writes the gpe0 register values in power state
+ * cbmem variable. After system wakes from sleep state internal PMC logic
+ * writes default values in GPE_CFG register which gives a wrong offset to
+ * calculate the wake reason. So we need to set it again to the routing
+ * table as per the devicetree.
+ */
+void pmc_fixup_power_state(void)
+{
+	int i;
+	struct chipset_power_state *ps;
+
+	ps = cbmem_find(CBMEM_ID_POWER_STATE);
+	if (ps == NULL)
+		return;
+
+	for (i = 0; i < GPE0_REG_MAX; i++) {
+		ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
+		ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
+		printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
+		       i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
+	}
+}
+
+/* Reads and prints ACPI specific PM registers */
+int pmc_fill_power_state(struct chipset_power_state *ps)
+{
+	int i;
+
+	ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+	ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+	ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+
+	printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
+	       ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
+
+	for (i = 0; i < GPE0_REG_MAX; i++) {
+		ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i));
+		ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i));
+		printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n",
+		       i, ps->gpe0_sts[i], i, ps->gpe0_en[i]);
+	}
+
+	soc_fill_power_state(ps);
+
+	ps->prev_sleep_state = pmc_prev_sleep_state(ps);
+	printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
+
+	return ps->prev_sleep_state;
+}
+
+/*
+ * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
+ * This lock is reset on cold boot, hard reset, soft reset and Sx.
+ */
+void pmc_global_reset_lock(void)
+{
+	/* Read PMC base address from soc */
+	uintptr_t etr = soc_read_pmc_base() + ETR;
+	uint32_t reg;
+
+	reg = read32((void *)etr);
+	if (reg & CF9_LOCK)
+		return;
+	reg |= CF9_LOCK;
+	write32((void *)etr, reg);
+}
+
+/*
+ * Enable or disable global reset. If global reset is enabled, hard reset and
+ * soft reset will trigger global reset, where both host and TXE are reset.
+ * This is cleared on cold boot, hard reset, soft reset and Sx.
+ */
+void pmc_global_reset_enable(bool enable)
+{
+	/* Read PMC base address from soc */
+	uintptr_t etr = soc_read_pmc_base() + ETR;
+	uint32_t reg;
+
+	reg = read32((void *)etr);
+	reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
+	write32((void *)etr, reg);
+}
+
+int vboot_platform_is_resuming(void)
+{
+	if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+		return 0;
+
+	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
+
+/* Read and clear GPE status (defined in arch/acpi.h) */
+int acpi_get_gpe(int gpe)
+{
+	int bank;
+	uint32_t mask, sts;
+	struct stopwatch sw;
+	int rc = 0;
+
+	if (gpe < 0 || gpe > GPE_MAX)
+		return -1;
+
+	bank = gpe / 32;
+	mask = 1 << (gpe % 32);
+
+	/* Wait up to 1ms for GPE status to clear */
+	stopwatch_init_msecs_expire(&sw, 1);
+	do {
+		if (stopwatch_expired(&sw))
+			return rc;
+
+		sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
+		if (sts & mask) {
+			outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
+			rc = 1;
+		}
+	} while (sts & mask);
+
+	return rc;
+}
+
+/*
+ * The PM1 control is set to S5 when vboot requests a reboot because the power
+ * state code above may not have collected its data yet. Therefore, set it to
+ * S5 when vboot requests a reboot. That's necessary if vboot fails in the
+ * resume path and requests a reboot. This prevents a reboot loop where the
+ * error is continually hit on the failing vboot resume path.
+ */
+void vboot_platform_prepare_reboot(void)
+{
+	const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
+	outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
+}
+
+void poweroff(void)
+{
+	pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+
+	/*
+	 * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
+	 * to transition to S5 state. If halt is called in SMM, then it prevents
+	 * the SMI handler from being triggered and system never enters S5.
+	 */
+	if (!ENV_SMM)
+		halt();
+}
+
+void pmc_gpe_init(void)
+{
+	uint32_t gpio_cfg = 0;
+	uint32_t gpio_cfg_reg;
+	uint8_t dw0, dw1, dw2;
+
+	/* Read PMC base address from soc. This is implemented in soc */
+	uintptr_t pmc_bar = soc_read_pmc_base();
+
+	/*
+	 * Get the dwX values for pmc gpe settings.
+	 */
+	soc_get_gpe_configs(&dw0, &dw1, &dw2);
+
+	const uint32_t gpio_cfg_mask =
+	    (GPE0_DWX_MASK << GPE0_DW_SHIFT(0)) |
+	    (GPE0_DWX_MASK << GPE0_DW_SHIFT(1)) |
+	    (GPE0_DWX_MASK << GPE0_DW_SHIFT(2));
+
+	/* Making sure that bad values don't bleed into the other fields */
+	dw0 &= GPE0_DWX_MASK;
+	dw1 &= GPE0_DWX_MASK;
+	dw2 &= GPE0_DWX_MASK;
+
+	/*
+	 * Route the GPIOs to the GPE0 block. Determine that all values
+	 * are different, and if they aren't use the reset values.
+	 */
+	if (dw0 == dw1 || dw1 == dw2) {
+		printk(BIOS_INFO, "PMC: Using default GPE route.\n");
+		gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
+
+		dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK;
+		dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK;
+		dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK;
+	} else {
+		gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0);
+		gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1);
+		gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2);
+	}
+
+	gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
+	gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
+
+	write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
+
+	/* Set the routes in the GPIO communities as well. */
+	gpio_route_gpe(dw0, dw1, dw2);
+}