diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/gpio/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 37 |
2 files changed, 35 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index a1e98dbe7d..8879547514 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -53,4 +53,12 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR Starting with MTL SoC, the recommendation is to use PCR for locking down the GPIO configuration. +# Indicate if SoC supports 4 bits Pad Mode with PAD_CFG_DW0 registers +config SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS + bool + default n + help + SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser + is 4 bits to support Native Function 1 to 15. + endif diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index beff0a0f9b..3790ba41d8 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -5,6 +5,8 @@ #include <intelblocks/gpio.h> +#define _BIT_WIDTH(x) ((1 << (x)) - 1) + #define PAD_CFG0_TX_STATE_BIT 0 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) #define PAD_CFG0_RX_STATE_BIT 1 @@ -12,16 +14,31 @@ #define PAD_CFG0_TX_DISABLE (1 << 8) #define PAD_CFG0_RX_DISABLE (1 << 9) #define PAD_CFG0_MODE_SHIFT 10 -#define PAD_CFG0_MODE_MASK (7 << 10) -#define PAD_CFG0_MODE_GPIO (0 << 10) -#define PAD_CFG0_MODE_FUNC(x) ((x) << 10) -#define PAD_CFG0_MODE_NF1 (1 << 10) -#define PAD_CFG0_MODE_NF2 (2 << 10) -#define PAD_CFG0_MODE_NF3 (3 << 10) -#define PAD_CFG0_MODE_NF4 (4 << 10) -#define PAD_CFG0_MODE_NF5 (5 << 10) -#define PAD_CFG0_MODE_NF6 (6 << 10) -#define PAD_CFG0_MODE_NF7 (7 << 10) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS) +#define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(4) +#else +#define PAD_CFG0_MODE_BIT_WIDTH _BIT_WIDTH(3) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */ +#define PAD_CFG0_MODE_MASK (PAD_CFG0_MODE_BIT_WIDTH << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_FUNC(x) ((x) << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_GPIO PAD_CFG0_MODE_FUNC(0) +#define PAD_CFG0_MODE_NF1 PAD_CFG0_MODE_FUNC(1) +#define PAD_CFG0_MODE_NF2 PAD_CFG0_MODE_FUNC(2) +#define PAD_CFG0_MODE_NF3 PAD_CFG0_MODE_FUNC(3) +#define PAD_CFG0_MODE_NF4 PAD_CFG0_MODE_FUNC(4) +#define PAD_CFG0_MODE_NF5 PAD_CFG0_MODE_FUNC(5) +#define PAD_CFG0_MODE_NF6 PAD_CFG0_MODE_FUNC(6) +#define PAD_CFG0_MODE_NF7 PAD_CFG0_MODE_FUNC(7) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS) +#define PAD_CFG0_MODE_NF8 PAD_CFG0_MODE_FUNC(8) +#define PAD_CFG0_MODE_NF9 PAD_CFG0_MODE_FUNC(9) +#define PAD_CFG0_MODE_NF10 PAD_CFG0_MODE_FUNC(10) +#define PAD_CFG0_MODE_NF11 PAD_CFG0_MODE_FUNC(11) +#define PAD_CFG0_MODE_NF12 PAD_CFG0_MODE_FUNC(12) +#define PAD_CFG0_MODE_NF13 PAD_CFG0_MODE_FUNC(13) +#define PAD_CFG0_MODE_NF14 PAD_CFG0_MODE_FUNC(14) +#define PAD_CFG0_MODE_NF15 PAD_CFG0_MODE_FUNC(15) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS */ #define PAD_CFG0_ROUTE_MASK (0xF << 17) #define PAD_CFG0_ROUTE_NMI (1 << 17) #define PAD_CFG0_ROUTE_SMI (1 << 18) |