diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/pmc.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/romstage.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/pmc.c | 35 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 3 |
5 files changed, 49 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index 64de97ade1..2cf1f00220 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -27,4 +27,14 @@ #define GEN_PMCONF1 0x20 # define UART_EN (1 << 24) +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +# define SECOND_TO_STS (1 << 17) +# define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +# define TCO_LOCK (1 << 12) +# define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + #endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h index b797e8e82b..760905cd1a 100644 --- a/src/soc/intel/baytrail/baytrail/romstage.h +++ b/src/soc/intel/baytrail/baytrail/romstage.h @@ -47,6 +47,7 @@ void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, void asmlinkage romstage_after_car(void); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); +void tco_disable(void); #if CONFIG_ENABLE_BUILTIN_COM1 void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 118c3485cd..b8eeb41a06 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -3,3 +3,4 @@ romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c +romstage-y += pmc.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c new file mode 100644 index 0000000000..e689ccd527 --- /dev/null +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/io.h> +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/romstage.h> + +void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index f62aeac23f..37040695a6 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -29,7 +29,6 @@ #include <timestamp.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> -#include <baytrail/iosf.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> #include <baytrail/romstage.h> @@ -121,6 +120,8 @@ void romstage_common(struct romstage_params *params) program_base_addresses(); + tco_disable(); + byt_config_com1_and_enable(); console_init(); |