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-rw-r--r--src/soc/intel/common/block/cse/cse_lite.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 7daa35eb9b..c9e4e1f470 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -751,7 +751,7 @@ void cse_fw_sync(void *unused)
}
}
-#if CONFIG(SOC_INTEL_TIGERLAKE)
+#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE)
/*
* This needs to happen after the MRC cache write to avoid a 2nd
* memory training sequence.