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-rw-r--r--src/soc/intel/apollolake/include/soc/meminit.h2
-rw-r--r--src/soc/intel/cannonlake/lockdown.c4
-rw-r--r--src/soc/intel/skylake/lockdown.c4
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 3b0b507ddd..27b6556d12 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -72,7 +72,7 @@ enum {
/*
* ODT settings :
* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B,
- * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
+ * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
* and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
*
* Note that the enum values correspond to the interpreted UPD fields
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
index dba59014db..7a3b0c0130 100644
--- a/src/soc/intel/cannonlake/lockdown.c
+++ b/src/soc/intel/cannonlake/lockdown.c
@@ -60,8 +60,8 @@ static void dmi_lockdown_cfg(void)
* GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range.
* Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
+ * "0b": SPI
+ * "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 79f6f70987..1abe9cb884 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -57,8 +57,8 @@ static void dmi_lockdown_config(void)
* GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range.
* Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
+ * "0b": SPI
+ * "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}