5 files changed, 12 insertions, 22 deletions

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 77d259b21b..53094b19e8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -162,13 +162,6 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config SERIRQ_CONTINUOUS_MODE
-	bool
-	default n
-	help
-	  If you set this option to y, the serial IRQ machine will be
-	  operated in continuous mode.
-
 config SMM_RESERVED_SIZE
 	hex
 	default 0x200000
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cbbfaaaf06..1f32a3efa2 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -22,6 +22,7 @@
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <soc/acpi.h>
@@ -190,8 +191,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->PmConfigPwrBtnOverridePeriod =
 		config->PmConfigPwrBtnOverridePeriod;
 	params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
-	params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable;
-	params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
+	params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF;
+	params->SerialIrqConfigSirqMode =
+		config->serirq_mode == SERIRQ_CONTINUOUS;
 	params->SerialIrqConfigStartFramePulse =
 		config->SerialIrqConfigStartFramePulse;
 
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index f131a1a5df..a8ee064c19 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -24,6 +24,7 @@
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
 #include <stdint.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
@@ -428,13 +429,7 @@ struct soc_intel_skylake_config {
 		RESET_POWER_CYCLE_4S      = 4,
 	} PmConfigPwrCycDur;
 
-	/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
-	u8 SerialIrqConfigSirqEnable;
-
-	enum {
-		SERIAL_IRQ_QUIET_MODE      = 0,
-		SERIAL_IRQ_CONTINUOUS_MODE = 1,
-	} SerialIrqConfigSirqMode;
+	enum serirq_mode serirq_mode;
 
 	enum {
 		SERIAL_IRQ_FRAME_PULSE_4CLK = 0,
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index f4e17c640b..c9afeb40df 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -26,6 +26,7 @@
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <romstage_handoff.h>
@@ -418,8 +419,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Indicate whether platform supports Voltage Margining */
 	params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable;
 
-	params->PchSirqEnable = config->SerialIrqConfigSirqEnable;
-	params->PchSirqMode = config->SerialIrqConfigSirqMode;
+	params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
+	params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
 
 	params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init();
 
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 8d978222a2..ae6c144346 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -109,6 +109,8 @@ static void clock_gate_8254(struct device *dev)
 
 void lpc_soc_init(struct device *dev)
 {
+	const config_t *const config = dev->chip_info;
+
 	/* Legacy initialization */
 	isa_dma_init();
 	reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script);
@@ -117,10 +119,7 @@ void lpc_soc_init(struct device *dev)
 	lpc_enable_pci_clk_cntl();
 
 	/* Set LPC Serial IRQ mode */
-	if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
+	lpc_set_serirq_mode(config->serirq_mode);
 
 	/* Interrupt configuration */
 	pch_enable_ioapic(dev);