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-rw-r--r--src/soc/intel/apollolake/acpi/globalnvs.asl3
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl5
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h5
3 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 6431faee4a..4aad29c81a 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -42,6 +42,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
SCDP, 8, // 0x29 - SD_CD GPIO portid
SCDO, 8, // 0x2A - GPIO pad offset relative to the community
UIOR, 8, // 0x2B - UART debug controller init on S3 resume
+ EPCS, 8, // 0x2C - SGX Enabled status
+ EMNA, 64, // 0x2D - 0x34 EPC base address
+ ELNG, 64, // 0x35 - 0x3C EPC Length
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 823173f15f..97a25a296f 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -52,3 +52,8 @@ Scope (\_SB)
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
+
+/* SGX */
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
+#include <soc/intel/common/acpi/sgx.asl>
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 9a098003c4..dd0746b1dd 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2017 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -44,6 +44,9 @@ typedef struct global_nvs_t {
uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */
uint8_t uior; /* 0x2B - UART debug controller init on S3
resume */
+ uint8_t ecps; /* 0x2C - SGX Enabled status */
+ uint64_t emna; /* 0x2D - 0x34 EPC base address */
+ uint64_t elng; /* 0x35 - 0x3C EPC Length */
uint8_t unused[212];
/* ChromeOS specific (0x100 - 0xfff) */