diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/uart.h | 24 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 35 |
4 files changed, 65 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h new file mode 100644 index 0000000000..ed4c7f0127 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_UART_H +#define SOC_INTEL_COMMON_BLOCK_UART_H + +#include <arch/io.h> + +void uart_common_init(device_t dev, uintptr_t baseaddr, + uint32_t clk_m_val, uint32_t clk_n_val); + +#endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig new file mode 100644 index 0000000000..103659f4c4 --- /dev/null +++ b/src/soc/intel/common/block/uart/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_UART + bool + select SOC_INTEL_COMMON_BLOCK_LPSS + help + Intel Processor common UART support diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc new file mode 100644 index 0000000000..13f5da880f --- /dev/null +++ b/src/soc/intel/common/block/uart/Makefile.inc @@ -0,0 +1 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c
\ No newline at end of file diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c new file mode 100644 index 0000000000..729a31ba1e --- /dev/null +++ b/src/soc/intel/common/block/uart/uart.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <intelblocks/lpss.h> +#include <intelblocks/uart.h> + +void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, + uint32_t clk_n_val) +{ + /* Set UART base address */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); + + /* Enable memory access and bus master */ + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take UART out of reset */ + lpss_reset_release(baseaddr); + + /* Set M and N divisor inputs and enable clock */ + lpss_clk_update(baseaddr, clk_m_val, clk_n_val); +} |