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-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index a9ad1d804e..1775cae779 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -86,6 +86,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->PcieRpEnableMask = mask;
m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->EnableC6Dram = config->enable_c6dram;
+ /* Disable Cpu Ratio Override temporary. */
+ m_cfg->CpuRatio = 0;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)