diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/gpe.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 34 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmc.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/pmutil.c | 478 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/reset.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/smi.c | 17 |
10 files changed, 82 insertions, 472 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2d8838a497..cc516f32ad 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -72,6 +72,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index dc81161598..f02d8cf01b 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -22,6 +22,7 @@ #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/gpio.h> @@ -91,7 +92,7 @@ void bootblock_soc_early_init(void) enable_pmcbar(); /* Clear global reset promotion bit */ - global_reset_enable(0); + pmc_global_reset_enable(0); /* Prepare UART for serial console. */ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ec4662c7a8..af625a1d9e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -31,6 +31,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/itss.h> +#include <intelblocks/pmclib.h> #include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/itss.h> @@ -326,9 +327,9 @@ static void soc_final(void *data) rdev_munmap(&vbt_rdev, vbt); /* Disable global reset, just in case */ - global_reset_enable(0); + pmc_global_reset_enable(0); /* Make sure payload/OS can't trigger global reset */ - global_reset_lock(); + pmc_global_reset_lock(); } static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 5482ed379f..7dfb6f5bd2 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -136,4 +136,5 @@ #define GPE0_DW3_30 126 #define GPE0_DW3_31 127 +#define GPE_MAX GPE0_DW3_31 #endif diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 4744b89814..3be39554ed 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -21,6 +21,8 @@ #include <stdint.h> #include <compiler.h> #include <arch/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> /* ACPI_BASE_ADDRESS */ @@ -135,6 +137,7 @@ #define GPE0_B 1 #define GPE0_C 2 #define GPE0_D 3 +#define GPE_STD GPE0_A #define SATA_PME_STS (1 << 17) #define SMB_WAK_STS (1 << 16) #define AVS_PME_STS (1 << 14) @@ -176,9 +179,7 @@ # define CF9_GLB_RST (1 << 20) #define GPIO_GPE_CFG 0x1050 #define GPE0_DWX_MASK 0xf -#define GPE0_DW1_SHIFT 4 -#define GPE0_DW2_SHIFT 8 -#define GPE0_DW3_SHIFT 12 +#define GPE0_DW_SHIFT(x) (4 + 4*(x)) #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #define PMC_GPE_N_95_64 8 @@ -216,33 +217,6 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __packed; -int fill_power_state(struct chipset_power_state *ps); -int chipset_prev_sleep_state(struct chipset_power_state *ps); -/* Rewrite the gpe0 registers in cbmem to proper values as per routing table */ -void fixup_power_state(void); - -/* Power Management Utility Functions. */ -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -void clear_pmc_status(void); -void clear_gpi_gpe_sts(void); -uint32_t get_smi_en(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); -uintptr_t get_pmc_mmio_bar(void); -void pmc_gpe_init(void); - -void global_reset_enable(bool enable); -void global_reset_lock(void); - void pch_log_state(void); void enable_pm_timer_emulation(void); diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 051943460b..190f5fb15c 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -20,6 +20,7 @@ #include <device/pci_ids.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/gpio.h> #include <soc/pci_devs.h> @@ -128,7 +129,7 @@ static int choose_slp_s3_assertion_width(int width_usecs) static void set_slp_s3_assertion_width(int width_usecs) { uint32_t reg; - uintptr_t gen_pmcon3 = get_pmc_mmio_bar() + GEN_PMCON3; + uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3; int setting = choose_slp_s3_assertion_width(width_usecs); reg = read32((void *)gen_pmcon3); @@ -143,7 +144,7 @@ static void pmc_init(struct device *dev) /* Set up GPE configuration */ pmc_gpe_init(); - fixup_power_state(); + pmc_fixup_power_state(); pch_set_acpi_mode(); if (cfg != NULL) @@ -153,7 +154,7 @@ static void pmc_init(struct device *dev) pch_log_state(); /* Now that things have been logged clear out the PMC state. */ - clear_pmc_status(); + pmc_clear_status(); } static const struct device_operations device_ops = { diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index bf89a09726..e007da9512 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -20,20 +20,18 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cbmem.h> #include <cpu/x86/msr.h> -#include <rules.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_def.h> -#include <halt.h> #include <intelblocks/msr.h> +#include <intelblocks/pmclib.h> +#include <rules.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <device/device.h> -#include <device/pci.h> #include <timer.h> -#include <vboot/vboot_common.h> #include "chip.h" static uintptr_t read_pmc_mmio_bar(void) @@ -41,32 +39,14 @@ static uintptr_t read_pmc_mmio_bar(void) return PMC_BAR0; } -uintptr_t get_pmc_mmio_bar(void) +uintptr_t soc_read_pmc_base(void) { return read_pmc_mmio_bar(); } -static void print_num_status_bits(int num_bits, uint32_t status, - const char * const bit_names[]) +const char *const *soc_smi_sts_array(size_t *a) { - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static uint32_t print_smi_status(uint32_t smi_sts) -{ - static const char * const smi_sts_bits[] = { + static const char *const smi_sts_bits[] = { [BIOS_SMI_STS] = "BIOS", [LEGACY_USB_SMI_STS] = "LEGACY USB", [SLP_SMI_STS] = "SLP_SMI", @@ -90,188 +70,44 @@ static uint32_t print_smi_status(uint32_t smi_sts) [PMC_OCP_SMI_STS] = "OCP_CSE", }; - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; -} - -static uint32_t reset_smi_status(void) -{ - uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); - return smi_sts; + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; } -uint32_t clear_smi_status(void) +/* + * For APL/GLK this check for power button status if nothing else + * is indicating an SMI and SMIs aren't turned into SCIs. + * Apparently, there is no PM1 status bit in the SMI status + * register. That makes things difficult for + * determining if the power button caused an SMI. + */ +uint32_t soc_get_smi_status(uint32_t generic_sts) { - uint32_t sts = reset_smi_status(); - - /* - * Check for power button status if nothing else is indicating an SMI - * and SMIs aren't turned into SCIs. Apparently, there is no PM1 status - * bit in the SMI status register. That makes things difficult for - * determining if the power button caused an SMI. - */ - if (sts == 0 && !(inl(ACPI_BASE_ADDRESS + PM1_CNT) & SCI_EN)) { + if (generic_sts == 0 && !(inl(ACPI_BASE_ADDRESS + PM1_CNT) & SCI_EN)) { uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) - sts |= (1 << FAKE_PM1_SMI_STS); + generic_sts |= (1 << FAKE_PM1_SMI_STS); } - return print_smi_status(sts); -} - -uint32_t get_smi_en(void) -{ - return inl(ACPI_BASE_ADDRESS + SMI_EN); -} - -void enable_smi(uint32_t mask) -{ - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); -} - -void disable_smi(uint32_t mask) -{ - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); -} - -void enable_pm1_control(uint32_t mask) -{ - uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); -} - -void disable_pm1_control(uint32_t mask) -{ - uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char * const pm1_sts_bits[] = { - [0] = "TMROF", - [5] = "GBL", - [8] = "PWRBTN", - [10] = "RTC", - [11] = "PRBTNOR", - [13] = "USB", - [14] = "PCIEXPWAK", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; + return generic_sts; } -uint16_t clear_pm1_status(void) +const char *const *soc_tco_sts_array(size_t *a) { - return print_pm1_status(reset_pm1_status()); -} - -void enable_pm1(uint16_t events) -{ - outw(events, ACPI_BASE_ADDRESS + PM1_EN); -} - -static uint32_t print_tco_status(uint32_t tco_sts) -{ - static const char * const tco_sts_bits[] = { + static const char *const tco_sts_bits[] = { [3] = "TIMEOUT", [17] = "SECOND_TO", }; - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; -} - -static uint32_t reset_tco_status(void) -{ - uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - - outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS); - return tco_sts & tco_en; -} - -uint32_t clear_tco_status(void) -{ - return print_tco_status(reset_tco_status()); -} - -void enable_gpe(uint32_t mask) -{ - uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); - gpe0a_en |= mask; - outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0)); -} - -void disable_gpe(uint32_t mask) -{ - uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); - gpe0a_en &= ~mask; - outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0)); -} - -void disable_all_gpe(void) -{ - disable_gpe(~0); -} - -/* Clear the gpio gpe0 status bits in ACPI registers */ -void clear_gpi_gpe_sts(void) -{ - int i; - - for (i = 1; i < GPE0_REG_MAX; i++) { - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); - } -} - -static uint32_t reset_gpe_status(void) -{ - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(0)); - return gpe_sts; + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; } -static uint32_t print_gpe_sts(uint32_t gpe_sts) +const char *const *soc_gpe_sts_array(size_t *a) { - static const char * const gpe_sts_bits[] = { + static const char *const gpe_sts_bits[] = { [0] = "PCIE_SCI", [2] = "SWGPE", [3] = "PCIE_WAKE0", @@ -290,269 +126,61 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts) [17] = "SATA_PME", }; - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; -} - -uint32_t clear_gpe_status(void) -{ - return print_gpe_sts(reset_gpe_status()); + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; } -/* Read and clear GPE status (defined in arch/acpi.h) */ -int acpi_get_gpe(int gpe) +uint32_t soc_reset_tco_status(void) { - int bank; - uint32_t mask, sts; - struct stopwatch sw; - int rc = 0; - - if (gpe < 0 || gpe > GPE0_DW3_31) - return -1; - - bank = gpe / 32; - mask = 1 << (gpe % 32); - - /* Wait up to 1ms for GPE status to clear */ - stopwatch_init_msecs_expire(&sw, 1); - do { - if (stopwatch_expired(&sw)) - return rc; - - sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); - if (sts & mask) { - outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); - rc = 1; - } - } while (sts & mask); + uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - return rc; + outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS); + return tco_sts & tco_en; } -void clear_pmc_status(void) +void soc_clear_pm_registers(uintptr_t pmc_bar) { - uint32_t prsts; uint32_t gen_pmcon1; - uintptr_t pmc_bar0 = read_pmc_mmio_bar(); - - prsts = read32((void *)(pmc_bar0 + PRSTS)); - gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); + gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS); - write32((void *)(pmc_bar0 + PRSTS), prsts); -} - - -/* Return 0, 3, or 5 to indicate the previous sleep state. */ -int chipset_prev_sleep_state(struct chipset_power_state *ps) -{ - /* Default to S0. */ - int prev_sleep_state = ACPI_S0; - - if (ps->pm1_sts & WAK_STS) { - switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { - case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) - prev_sleep_state = ACPI_S3; - break; - case ACPI_S5: - prev_sleep_state = ACPI_S5; - break; - } - - /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); - } - return prev_sleep_state; + write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1 & ~RPS); } -/* - * This function re-writes the gpe0 register values in power state - * cbmem variable. After system wakes from sleep state internal PMC logic - * writes default values in GPE_CFG register which gives a wrong offset to - * calculate the wake reason. So we need to set it again to the routing - * table as per the devicetree. - */ -void fixup_power_state(void) +void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { - int i; - struct chipset_power_state *ps; + DEVTREE_CONST struct soc_intel_apollolake_config *config; - ps = cbmem_find(CBMEM_ID_POWER_STATE); - if (ps == NULL) + /* Look up the device in devicetree */ + DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; - - for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); - printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", - i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); } + config = dev->chip_info; + + /* Assign to out variable */ + *dw0 = config->gpe0_dw1; + *dw1 = config->gpe0_dw2; + *dw2 = config->gpe0_dw3; } -/* returns prev_sleep_state */ -int fill_power_state(struct chipset_power_state *ps) +void soc_fill_power_state(struct chipset_power_state *ps) { - int i; uintptr_t pmc_bar0 = read_pmc_mmio_bar(); - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3)); - ps->prev_sleep_state = chipset_prev_sleep_state(ps); - - printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", - ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n", - ps->prsts, ps->tco_sts); + ps->prsts, ps->tco_sts); printk(BIOS_DEBUG, - "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", - ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); - printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", - inl(ACPI_BASE_ADDRESS + SMI_EN), inl(ACPI_BASE_ADDRESS + SMI_STS)); - for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); - printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", - i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); - } - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps->prev_sleep_state; -} - -int vboot_platform_is_resuming(void) -{ - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) - return 0; - - return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; -} - -/* - * If possible, lock 0xcf9. Once the register is locked, it can't be changed. - * This lock is reset on cold boot, hard reset, soft reset and Sx. - */ -void global_reset_lock(void) -{ - uintptr_t etr = read_pmc_mmio_bar() + ETR; - uint32_t reg; - - reg = read32((void *)etr); - if (reg & CF9_LOCK) - return; - reg |= CF9_LOCK; - write32((void *)etr, reg); -} - -/* - * Enable or disable global reset. If global reset is enabled, hard reset and - * soft reset will trigger global reset, where both host and TXE are reset. - * This is cleared on cold boot, hard reset, soft reset and Sx. - */ -void global_reset_enable(bool enable) -{ - uintptr_t etr = read_pmc_mmio_bar() + ETR; - uint32_t reg; - - reg = read32((void *)etr); - reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; - write32((void *)etr, reg); -} - -/* - * The PM1 control is set to S5 when vboot requests a reboot because the power - * state code above may not have collected its data yet. Therefore, set it to - * S5 when vboot requests a reboot. That's necessary if vboot fails in the - * resume path and requests a reboot. This prevents a reboot loop where the - * error is continually hit on the failing vboot resume path. - */ -void vboot_platform_prepare_reboot(void) -{ - const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT; - outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port); -} - -void poweroff(void) -{ - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - - /* - * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM - * to transition to S5 state. If halt is called in SMM, then it prevents - * the SMI handler from being triggered and system never enters S5. - */ - if (!ENV_SMM) - halt(); -} - -void pmc_gpe_init(void) -{ - uint32_t gpio_cfg = 0; - uint32_t gpio_cfg_reg; - uint8_t dw1, dw2, dw3; - DEVTREE_CONST struct soc_intel_apollolake_config *config; - - /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); - return; - } - config = dev->chip_info; - - uintptr_t pmc_bar = get_pmc_mmio_bar(); - - const uint32_t gpio_cfg_mask = - (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | - (GPE0_DWX_MASK << GPE0_DW3_SHIFT); - - /* Assign to local variable */ - dw1 = config->gpe0_dw1; - dw2 = config->gpe0_dw2; - dw3 = config->gpe0_dw3; - - /* Making sure that bad values don't bleed into the other fields */ - dw1 &= GPE0_DWX_MASK; - dw2 &= GPE0_DWX_MASK; - dw3 &= GPE0_DWX_MASK; - - /* Route the GPIOs to the GPE0 block. Determine that all values - * are different, and if they aren't use the reset values. - * DW0 is reserved/unused */ - if (dw1 == dw2 || dw2 == dw3) { - printk(BIOS_INFO, "PMC: Using default GPE route.\n"); - gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); - - dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK; - dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK; - dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK; - } else { - gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT; - gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT; - gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT; - } - - gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; - gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; - - write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); - - /* Set the routes in the GPIO communities as well. */ - gpio_route_gpe(dw1, dw2, dw3); + "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", + ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); } void enable_pm_timer_emulation(void) @@ -566,7 +194,7 @@ void enable_pm_timer_emulation(void) * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); wrmsr(MSR_EMULATE_PM_TMR, msr); } diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 15e78fe203..6ea7a5998e 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <delay.h> #include <fsp/util.h> +#include <intelblocks/pmclib.h> #include <reset.h> #include <soc/heci.h> #include <soc/pm.h> @@ -25,8 +26,8 @@ void do_global_reset(void) { - global_reset_enable(1); - do_hard_reset(); + pmc_global_reset_enable(1); + hard_reset(); } void soc_reset_prepare(enum reset_type reset_type) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9dad15fc3a..59278a6942 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -33,6 +33,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/systemagent.h> +#include <intelblocks/pmclib.h> #include <reset.h> #include <soc/cpu.h> #include <soc/intel/common/mrc_cache.h> @@ -231,7 +232,7 @@ asmlinkage void car_stage_entry(void) console_init(); - s3wake = fill_power_state(ps) == ACPI_S3; + s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (punit_init()) diff --git a/src/soc/intel/apollolake/smi.c b/src/soc/intel/apollolake/smi.c index cf1b386109..f506aef63d 100644 --- a/src/soc/intel/apollolake/smi.c +++ b/src/soc/intel/apollolake/smi.c @@ -22,6 +22,7 @@ #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#include <intelblocks/pmclib.h> #include <string.h> #include <soc/pm.h> #include <soc/smm.h> @@ -30,7 +31,7 @@ void southbridge_smm_clear_state(void) { printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - if (get_smi_en() & APMC_EN) { + if (pmc_get_smi_en() & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } @@ -38,21 +39,21 @@ void southbridge_smm_clear_state(void) printk(BIOS_DEBUG, "Done\n"); /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_gpe_status(); } void southbridge_smm_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ - enable_pm1(PWRBTN_EN | GBL_EN); - disable_gpe(PME_B0_EN); + pmc_enable_pm1(PWRBTN_EN | GBL_EN); + pmc_disable_gpe(PME_B0_EN); /* Enable SMI generation */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN); + pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |