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Diffstat (limited to 'src/soc/intel/xeon_sp/romstage.c')
-rw-r--r--src/soc/intel/xeon_sp/romstage.c28
1 files changed, 2 insertions, 26 deletions
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index a519663134..9d3665c9fe 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -18,9 +18,9 @@
#include <intelblocks/rtc.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <fsp/util.h>
#include <soc/romstage.h>
-#include <soc/soc_util.h>
-#include "chip.h"
+#include <soc/util.h>
asmlinkage void car_stage_entry(void)
{
@@ -55,27 +55,3 @@ asmlinkage void car_stage_entry(void)
run_postcar_phase(&pcf);
}
-
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
-{
-}
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
- const config_t *config = config_of_soc();
- FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
- mupd->FspmUpdVersion = FSP_UPD_VERSION;
-
- // ErrorLevel - 0 (disable) to 8 (verbose)
- m_cfg->PcdFspMrcDebugPrintErrorLevel = 0;
- m_cfg->PcdFspKtiDebugPrintErrorLevel = 0;
-
- soc_memory_init_params(m_cfg);
-
- mainboard_memory_init_params(mupd);
-
- m_cfg->VTdConfig.VTdSupport = config->vtd_support;
- m_cfg->VTdConfig.CoherencySupport = config->coherency_support;
- m_cfg->VTdConfig.ATS = config->ats_support;
-}