diff options
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/cpu.c | 31 | ||||
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 1 |
2 files changed, 0 insertions, 32 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 4afe47cbff..5bde819ec6 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -205,34 +205,3 @@ void cpx_init_cpus(struct device *dev) /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); } - -msr_t read_msr_ppin(void) -{ - msr_t ppin = {0}; - msr_t msr; - - /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & MSR_PPIN_CAP) == 0) { - printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); - return ppin; - } - - /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ - msr = rdmsr(MSR_PPIN_CTL); - if (msr.lo & MSR_PPIN_CTL_LOCK) { - printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); - return ppin; - } - - if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { - /* Set MSR_PPIN_CTL ENABLE to 1 */ - msr.lo |= MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - } - ppin = rdmsr(MSR_PPIN); - /* Set enable to 0 after reading MSR_PPIN */ - msr.lo &= ~MSR_PPIN_CTL_ENABLE; - wrmsr(MSR_PPIN_CTL, msr); - return ppin; -} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 19f6e4c5d5..693de8fbcc 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -10,6 +10,5 @@ #define CPUID_COOPERLAKE_SP_A1 0x05065b void cpx_init_cpus(struct device *dev); -msr_t read_msr_ppin(void); #endif |