aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/xeon_sp/cpx/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/romstage.c')
-rw-r--r--src/soc/intel/xeon_sp/cpx/romstage.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index 96949fd8af..6c65994412 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -3,6 +3,7 @@
#include <arch/romstage.h>
#include <fsp/api.h>
#include <soc/romstage.h>
+#include <soc/pci_devs.h>
#include "chip.h"
void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
@@ -13,6 +14,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
+ const struct device *dev;
/* ErrorLevel - 0 (disable) to 8 (verbose) */
m_cfg->DebugPrintLevel = 8;
@@ -61,5 +63,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->PEXPHIDE = 0x0;
m_cfg->HidePEXPMenu = 0x0;
+ /* Enable PCH thermal device in FSP, the definition of ThermalDeviceEnable is
+ 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI mode */
+ dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
+ m_cfg->ThermalDeviceEnable = dev && dev->enabled;
+
mainboard_memory_init_params(mupd);
}