2 files changed, 36 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl
new file mode 100644
index 0000000000..0d62edd926
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/pmc.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+Scope (\_SB.PCI0) {
+
+	Device (PMC)
+	{
+		Name (_HID, "INTC1026")
+		Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
+		/*
+		 * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF.
+		 * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR.
+		 */
+		Name (_CRS, ResourceTemplate () {
+			Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000)
+		})
+	}
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 8593d07326..9d25a735f5 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2019-2020 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -40,6 +40,9 @@
 /* PCIE Ports */
 #include "pcie.asl"
 
+/* pmc 0:1f.2 */
+#include "pmc.asl"
+
 /* Serial IO */
 #include "serialio.asl"