diff options
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 24 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d23148aac8..9fc70f8a46 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -122,6 +122,14 @@ struct soc_intel_tigerlake_config { * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; + /* PCIe RP L1 substate */ + enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, + } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 14997c519a..7230a4c7e0 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -28,6 +28,25 @@ #include <soc/soc_chip.h> #include <string.h> +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_tigerlake_config *config; @@ -113,6 +132,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } } + /* RP Configs */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + params->PcieRpL1Substates[i] = + get_l1_substate_control(config->PcieRpL1Substates[i]); + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); if (dev) { |