diff options
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 2 |
2 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f0858db1b8..e729e8c0ee 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -272,9 +272,6 @@ struct soc_intel_tigerlake_config { /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* Gfx related */ uint8_t SkipExtGfxScan; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 40683e2a2e..24b8575357 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -130,7 +130,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ m_cfg->ChHashMask = 0x30CC; /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT; |