diff options
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/romstage.h | 25 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/soc_chip.h | 21 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/systemagent.h | 50 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/Makefile.inc | 20 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 22 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/pch.c | 27 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/romstage.c | 128 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/systemagent.c | 48 |
8 files changed, 341 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h new file mode 100644 index 0000000000..046e856920 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/api.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); +void pch_init(void); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/soc_chip.h b/src/soc/intel/tigerlake/include/soc/soc_chip.h new file mode 100644 index 0000000000..3b02386375 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/soc_chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_SOC_CHIP_H_ +#define _SOC_TIGERLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_TIGERLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h new file mode 100644 index 0000000000..56a2bd8887 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#ifndef SOC_TIGERLAKE_SYSTEMAGENT_H +#define SOC_TIGERLAKE_SYSTEMAGENT_H + +#include <intelblocks/systemagent.h> + +/* Device 0:0.0 PCI configuration space */ + +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define BIOS_RESET_CPL 0x5da8 +#define EDRAMBAR 0x5408 +#define REGBAR 0x5420 + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + +#endif diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc new file mode 100644 index 0000000000..8d151e3871 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c new file mode 100644 index 0000000000..810cff4a20 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <soc/romstage.h> + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + /* TODO: Update with UPD override as FSP matures */ +} diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c new file mode 100644 index 0000000000..88a7cc7163 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/smbus.h> +#include <intelblocks/tco.h> +#include <soc/romstage.h> + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c new file mode 100644 index 0000000000..17efc98fac --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <intelblocks/cfg.h> +#include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> +#include <soc/iomap.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/soc_chip.h> +#include <string.h> + +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + +/* Save the DIMM information for SMBIOS table 17 */ +static void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (src_dimm->Status != DIMM_PRESENT) + continue; + + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} + +void mainboard_romstage_entry(void) +{ + bool s3wake; + struct chipset_power_state *ps = pmc_get_power_state(); + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + /* Program PCH init */ + pch_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); + + s3wake = pmc_fill_power_state(ps) == ACPI_S3; + fsp_memory_init(s3wake); + pmc_set_disb(); + if (!s3wake) + save_dimm_info(); +} diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c new file mode 100644 index 0000000000..183089e9fb --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/systemagent.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is created based on Intel Tiger Lake Processor SA Datasheet + * Document number: 571131 + * Chapter number: 3 + */ + +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/systemagent.h> + +void systemagent_early_init(void) +{ + static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + }; + + static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = { + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + /* Set Fixed MMIO address into PCI configuration space */ + sa_set_pci_bar(soc_fixed_pci_resources, + ARRAY_SIZE(soc_fixed_pci_resources)); + /* Set Fixed MMIO address into MCH base address */ + sa_set_mch_bar(soc_fixed_mch_resources, + ARRAY_SIZE(soc_fixed_mch_resources)); + /* Enable PAM registers */ + enable_pam_region(); +} |