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path: root/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
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Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params_tgl.c')
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index c5629a51c6..b46f3a3f10 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -89,6 +89,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
else
m_cfg->InternalGfx = 0x1;
+ /* ISH */
+ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
+ if (!dev || !dev->enabled)
+ m_cfg->PchIshEnable = 0;
+ else
+ m_cfg->PchIshEnable = 1;
+
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;