diff options
Diffstat (limited to 'src/soc/intel/tigerlake/include/soc/gpio.h')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/gpio.h | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index ccc274ba3e..3a39e3a153 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2020 Intel Corp. + * Copyright 2020 The coreboot project Authors * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,9 +19,21 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#define CROS_GPIO_COMM0_NAME "INT34C5:00" -#define CROS_GPIO_COMM1_NAME "INT34C5:01" -#define CROS_GPIO_COMM4_NAME "INT34C5:02" -#define CROS_GPIO_COMM5_NAME "INT34C5:03" +#if CONFIG(SOC_INTEL_TIGERLAKE) + + #define CROS_GPIO_NAME "INT34C5" + #define CROS_GPIO_COMM0_NAME "INT34C5:00" + #define CROS_GPIO_COMM1_NAME "INT34C5:01" + #define CROS_GPIO_COMM4_NAME "INT34C5:02" + #define CROS_GPIO_COMM5_NAME "INT34C5:03" + +#elif CONFIG(SOC_INTEL_JASPERLAKE) + + #define CROS_GPIO_NAME "INT34C8" + #define CROS_GPIO_COMM0_NAME "INT34C8:00" + #define CROS_GPIO_COMM1_NAME "INT34C8:01" + #define CROS_GPIO_COMM4_NAME "INT34C8:02" + #define CROS_GPIO_COMM5_NAME "INT34C8:03" +#endif #endif |