aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/tigerlake/fsp_params_tgl.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params_tgl.c')
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index f3f700f146..a8be407d23 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -186,6 +186,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable Hybrid storage auto detection */
params->HybridStorageMode = config->HybridStorageMode;
+ /* USB4/TBT */
+ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
+ dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
+ if (dev)
+ params->ITbtPcieRootPortEn[i] = dev->enabled;
+ else
+ params->ITbtPcieRootPortEn[i] = 0;
+ }
+
mainboard_silicon_init_params(params);
}