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Diffstat (limited to 'src/soc/intel/tigerlake/bootblock')
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 18ca5e51af..5c4d1d5fb7 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -67,11 +67,16 @@ static void soc_config_pwrmbase(void)
void bootblock_pch_early_init(void)
{
- fast_spi_early_init(SPI_BASE_ADDRESS);
- gspi_early_bar_init();
+ /*
+ * Perform P2SB configuration before any another controller initialization as the
+ * controller might want to perform PCR settings.
+ */
p2sb_enable_bar();
p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS);
+ gspi_early_bar_init();
+
/*
* Enabling PWRM Base for accessing
* Global Reset Cause Register.