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-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index cd264d682c..33637e9e01 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -169,6 +169,11 @@ void pch_early_iorange_init(void)
* value program in ESPI PCI offset 82h.
*/
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ /*
+ * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
+ * value programmed in LPC PCI offset 80h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
}
/* Program generic IO Decode Range */