3 files changed, 10 insertions, 8 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 14d4fa1781..55e74cd360 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -241,6 +241,9 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 	int
 	default 120
 
+config CPU_XTAL_HZ
+	default 24000000
+
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index f1b40f6d01..5ec002322b 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -169,15 +169,17 @@ static void configure_c_states(void)
  */
 static void enable_pm_timer_emulation(void)
 {
-	/* ACPI PM timer emulation */
 	msr_t msr;
+
+	if (!CONFIG_CPU_XTAL_HZ)
+		return;
+
 	/*
 	 * The derived frequency is calculated as follows:
-	 *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
-	 * Back solve the multiplier so the 3.579545MHz ACPI timer
-	 * frequency is used.
+	 * (clock * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
 	 */
-	msr.hi = (3579545ULL << 32) / CTC_FREQ;
+	msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
 	/* Set PM1 timer IO port and enable */
 	msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 			EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 740b3d3fb0..473068c210 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -25,9 +25,6 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
-/* Common Timer Copy (CTC) frequency - 24MHz. */
-#define CTC_FREQ		24000000
-
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \