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-rw-r--r--src/soc/intel/skylake/bootblock/pch.c17
-rw-r--r--src/soc/intel/skylake/lpc.c10
2 files changed, 2 insertions, 25 deletions
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index a5bbb095b0..9fb2aa1b36 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -129,21 +129,8 @@ void pch_early_iorange_init(void)
}
/* IO Decode Enable */
- if (pch_check_decode_enable() == 0) {
- io_enables = lpc_enable_fixed_io_ranges(io_enables);
- /*
- * As per PCH BWG 2.5.1.6.
- * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
- * value programmed in LPC PCI offset 82h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
- /*
- * As per PCH BWG 2.5.1.5.
- * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
- * value programmed in LPC PCI offset 80h.
- */
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
- }
+ if (pch_check_decode_enable() == 0)
+ lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 6a22af8216..5abae765c9 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -7,7 +7,6 @@
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <soc/iomap.h>
#include <soc/pcr_ids.h>
@@ -25,15 +24,6 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
gen_io_dec[3] = config->gen4_dec;
}
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
- /* Mirror these same settings in DMI PCR */
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
- pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
static const struct reg_script pch_misc_init_script[] = {
/* Enable BIOS updates outside of SMM */
REG_PCI_RMW8(0xdc, ~(1 << 5), 0),