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-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/pmutil.c4
-rw-r--r--src/soc/intel/skylake/systemagent.c4
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d120d1e474..70d12e4316 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -240,7 +240,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
}
- params->GraphicsConfigPtr = (u32) vbt_data;
+ params->GraphicsConfigPtr = (u32)vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index fe26ebfe37..d411c762df 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -136,12 +136,12 @@ uint8_t *pmc_mmio_regs(void)
/* 4KiB alignment. */
reg32 &= ~0xfff;
- return (void *)(uintptr_t) reg32;
+ return (void *)(uintptr_t)reg32;
}
uintptr_t soc_read_pmc_base(void)
{
- return (uintptr_t) (pmc_mmio_regs());
+ return (uintptr_t)(pmc_mmio_regs());
}
uint32_t *soc_pmc_etr_addr(void)
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index 6186734d7e..d203bdadff 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -84,9 +84,9 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
{
msr_t msr;
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
- *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
+ *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
- *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
+ *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
return 0;
}