diff options
Diffstat (limited to 'src/soc/intel/skylake')
23 files changed, 46 insertions, 46 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 53e6b3c0a8..26a131ddc2 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -182,15 +182,15 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* CPU core count */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) +#if CONFIG(CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -207,7 +207,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); } @@ -275,7 +275,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->mon_alrm = 0x00; fadt->century = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; - if (!IS_ENABLED(CONFIG_NO_FADT_8042)) + if (!CONFIG(NO_FADT_8042)) fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index ebf4289218..8788bd3e93 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -78,7 +78,7 @@ Device (GPIO) */ Method (GADD, 1, NotSerialized) { -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) /* GPIO Community 0 */ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) { diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0c4decc186..0aba2e7542 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -74,6 +74,6 @@ Method (_OSC, 4) } /* SGX */ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index e766fd767f..ad68ef90cf 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -112,7 +112,7 @@ Device (EMMC) } } -#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE) +#if !CONFIG(EXCLUDE_NATIVE_SD_INTERFACE) Device (SDXC) { Name (_ADR, 0x001E0006) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index acf25ffd48..4358fba40f 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -32,14 +32,14 @@ void bootblock_soc_early_init(void) bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } void bootblock_soc_init(void) { /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + if (CONFIG(PLATFORM_USES_FSP1_1)) bootblock_fsp_temp_ram_init(); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 34cc713124..0f6c8a85d4 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -71,7 +71,7 @@ static void soc_config_acpibase(void) */ reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); else pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0); @@ -105,7 +105,7 @@ static void soc_config_pwrmbase(void) pcr_write32(PID_DMI, PCR_DMI_PMBASEA, ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); else pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); @@ -131,7 +131,7 @@ void pch_early_iorange_init(void) LPC_IOE_EC_62_66; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + if (CONFIG(DRIVERS_UART_8250IO)) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 1f32a3efa2..98e5baf483 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -60,7 +60,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif @@ -68,7 +68,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .init = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e43aa833f4..15eb6b2651 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -194,7 +194,7 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif @@ -205,7 +205,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif }; @@ -323,7 +323,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; - params->CpuConfig.Bits.VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); + params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 910dcb88c9..0ff5a137c6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -489,7 +489,7 @@ static void post_mp_init(void) smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) smm_lock(); #endif diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 4da705da73..3d66fa4602 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -41,7 +41,7 @@ static const struct pad_group skl_community_com0_groups[] = { static const struct pad_group skl_community_com1_groups[] = { INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */ -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */ @@ -54,7 +54,7 @@ static const struct pad_group skl_community_com1_groups[] = { }; static const struct pad_group skl_community_com3_groups[] = { -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ @@ -86,7 +86,7 @@ static const struct pad_community skl_gpio_communities[] = { }, { .port = PID_GPIOCOM1, .first_pad = GPP_C0, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, #else .last_pad = GPP_E23, @@ -105,7 +105,7 @@ static const struct pad_community skl_gpio_communities[] = { .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -159,7 +159,7 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) { GPP_E, GPP_E}, { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, #endif @@ -172,7 +172,7 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 1bf6ba410c..07ee67ab88 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -59,9 +59,9 @@ void graphics_soc_init(struct device *dev) * In case of non-FSP solution, SoC need to select another * Kconfig to perform GFX initialization. */ - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) { + if (CONFIG(RUN_FSP_GOP)) { /* nothing to do */ - } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + } else if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { int lightup_ok; gma_gfxinit(&lightup_ok); @@ -101,7 +101,7 @@ uintptr_t graphics_soc_write_acpi_opregion(struct device *device, global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) + if (!CONFIG(INTEL_GMA_ADD_VBT)) return current; /* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index f5065148d3..74328b217e 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -18,7 +18,7 @@ #include <intelblocks/systemagent.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #include <fsp/bootblock.h> #else static inline void bootblock_fsp_temp_ram_init(void) {} diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 137b37e613..1c143a2c43 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -18,7 +18,7 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> #else # include <soc/gpio_soc_defs.h> diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 24bc2a8c1d..615edac097 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -173,7 +173,7 @@ struct chipset_power_state { * This is used only in FSP1_1 as we wanted to keep the flow unchanged. * Internally fill_power_state calls the new pmc_fill_power_state now */ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 8195440952..72992d2517 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,7 +48,7 @@ struct smm_relocation_params { int smm_save_state_in_msrs; }; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 064ec3118f..465e248700 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -19,7 +19,7 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) #include <fsp/soc_binding.h> #else #include <fsp/api.h> @@ -69,7 +69,7 @@ struct vr_config { #define VR_CFG_AMP(i) ((i) * 4) -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 63ff18d406..f7aa584f37 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -239,7 +239,7 @@ static void print_me_version(void *unused) * Print ME version only if UART debugging is enabled. Else, it takes ~1 * second to talk to ME and get this information. */ - if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (!CONFIG(CONSOLE_SERIAL)) return; hfs.data = me_read_config32(PCI_ME_HFSTS1); diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index bca151e522..60a7070408 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -31,7 +31,7 @@ size_t mmap_region_granularity(void) { - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) + if (CONFIG(HAVE_SMI_HANDLER)) /* Align to TSEG size when SMM is in use */ if (CONFIG_SMM_TSEG_SIZE != 0) return CONFIG_SMM_TSEG_SIZE; @@ -142,7 +142,7 @@ static size_t get_prmrr_size(uintptr_t dram_base, uintptr_t prmrr_base = dram_base; size_t prmrr_size; - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + if (CONFIG(PLATFORM_USES_FSP1_1)) prmrr_size = 1*MiB; else prmrr_size = config->PrmrrSize; @@ -186,7 +186,7 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, traditional_mem_base -= sa_get_tseg_size(); /* Get DPR size */ - if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + if (CONFIG(SA_ENABLE_DPR)) traditional_mem_base -= sa_get_dpr_size(); /* Traditional Area Size */ diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index 9482456922..ee04f0272d 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -28,7 +28,7 @@ car_stage_entry: .Lhlt: xchg %al, %ah -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e147f0c0aa..dc9c528c06 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -88,7 +88,7 @@ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index c1a0b97cb2..43ba9c9c6f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -166,7 +166,7 @@ asmlinkage void car_stage_entry(void) top_of_ram -= 16*MiB; postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { void *smm_base; size_t smm_size; uintptr_t tseg_base; @@ -225,7 +225,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->RMT = config->Rmt; m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) @@ -281,7 +281,7 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index e402ba5e8d..2e93075f7b 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -27,7 +27,7 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 89169d0e7c..905154e8ac 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -127,7 +127,7 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { .icc_max = VR_CFG_AMP(34), .voltage_limit = 1520, }, -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#if CONFIG(PLATFORM_USES_FSP1_1) [VR_RING] = { .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), @@ -240,7 +240,7 @@ void fill_vr_domain_config(void *params, vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) +#if CONFIG(PLATFORM_USES_FSP2_0) vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; #endif |